US3654441A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Four-phase high speed counter
Assignee: RCA Corp
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Filing: 1970-11-16
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Granted: 1972-04-04
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Expires: 1990-11-16
Abstract
Abstract In response to each pulse to be counted, the bit stored in each stage of the counter is sensed. In the case of up-counting, when the j least significant bits are 1 and the j + 1th least significant bit is a 0, the stages storing these j + 1 bits are caused concurrently to change state, and where j is any integer which is less than n, and n is the number of stages in the counter. In the case of down-counting, the same procedure is followed for the complementary case. The counter may be implemented with metal oxide semiconductor (MOS) field-effect transistors.
Inventors
- 👤 Uipalananda Bharali
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:09
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/001
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
231 words
A counter comprising, in combination: a plurality of stages, each for storing a binary digit of different rank, each such stage having an input terminal to which a first voltage level may be applied for changing the state of that stage and to which a second voltage level may be applied for maintaining that stage in the same state and each such stage having an output terminal; a plurality of switches, one for each stage except the last stage, each switch connected between the input terminal of its stage and the input terminal of the following stage; means at each stage except the last stage for closing the switch of that stage in response to the storage there of a bit of one value and for opening the switch of that stage in response to the storage there of a bit of other value; a plurality of storage means, one per input terminal, each connected between its input terminal and a point at said first voltage level; means coupled to all of said storage means for concurrently charging them to said second voltage level during a first interval of time; and means responsive to a counter input signal for connecting, during a following interval of time, the input terminal of the one of said stages storing the binary digit of least significance to a circuit point at said first voltage level.
Claim 2
Dependent Claim
231 words
A counter comprising, in combination: a plurality of stages, each for storing a binary digit of different rank, each such stage having an input terminal to which a first voltage level may be applied for changing the state of that stage and to which a second voltage level may be applied for maintaining that stage in the same state and each such stage having an output terminal; a plurality of switches, one for each stage except the last stage, each switch connected between the input terminal of its stage and the input terminal of the following stage; means at each stage except the last stage for closing the switch of that stage in response to the storage there of a bit of one value and for opening the switch of that stage in response to the storage there of a bit of other value; a plurality of storage means, one per input terminal, each connected between its input terminal and a point at said first voltage level; means coupled to all of said storage means for concurrently charging them to said second voltage level during a first interval of time; and means responsive to a counter input signal for connecting, during a following interval of time, the input terminal of the one of said stages storing the binary digit of least significance to a circuit point at said first voltage level.
Claim 3
Dependent Claim
42 words
A counter set forth in claim 1 wherein each switch comprises a field-effect device the conduction path of which is connected between a pair of said input terminals and the gate electrode of which is connected to one of said output terminals.
Claim 4
Dependent Claim
31 words
A counter as set forth in claim 2 wherein said counter is an integrated circuit on a common substrate and wherein each storage means comprises a distributed capacitance to said substrate.
Claim 5
Dependent Claim
157 words
In the counter of the type in which, when more than one stage is required to change state, said more than one stages change state concurrently, in combination: N stages, where N is an integer substantially greater than 1 and is equal to the number of bits the counter is capable of storing, each such stage having an input terminal and an output terminal; and N-1 switches, one for each stage except the Nth stage, each switch having a control element and a path between two terminals whose impedance is controlled solely by said control element, the switch for each jth stage connected at its control element to the output terminal of the jth stage and responsive to the bit stored therein, connected at one switch terminal to the input terminal of the jth stage, and connected at its other switch terminal to the input terminal to the j+1th stage, where j 1, 2, ...(N - 1).
Claim 6
Dependent Claim
157 words
In the counter of the type in which, when more than one stage is required to change state, said more than one stages change state concurrently, in combination: N stages, where N is an integer substantially greater than 1 and is equal to the number of bits the counter is capable of storing, each such stage having an input terminal and an output terminal; and N-1 switches, one for each stage except the Nth stage, each switch having a control element and a path between two terminals whose impedance is controlled solely by said control element, the switch for each jth stage connected at its control element to the output terminal of the jth stage and responsive to the bit stored therein, connected at one switch terminal to the input terminal of the jth stage, and connected at its other switch terminal to the input terminal to the j+1th stage, where j 1, 2, ...(N - 1).
Claim 7
Dependent Claim
41 words
In a counter as set forth in claim 4, each switch comprising a field-effect transistor having a gate electrode comprising said control element and having a conduction path at the opposite ends of which said two switch terminals are respectively located.
References Cited (Backward Citations)
US3121787A
Cited
US3422254A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-04-04 | 1975-10-04 | 1976-04-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-04-04 | 1979-10-04 | 1980-04-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-04-04 | 1983-10-04 | 1984-04-04 | $7700.00 | Window Closed / Lapsed |