US3653036A
Expired / Lapsed
US
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Information handling system especially for magnetic recording and reproducing of digital data
Assignee: General Dynamics Corp
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Filing: 1969-11-14
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Granted: 1972-03-28
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Expires: 1989-11-14
Abstract
Abstract A system for storage on a magnetic record medium (tape or disc) of data with an extremely high packing density is described. Binary input information is encoded into a ternary signal for recording. That ternary signal has spectral properties which facilitate recording with extremely high bit packing density. The ternary signal also contains timing information. On playback the signal is decoded into binary coded ternary form. Timing information with respect to words of ternary data, as well as the individual terts which make up the words, is also derived. The system includes mans for synchronizing the reproduced data in accordance with the timing information derived from the data itself, as well as with an external clock, and decodes the data into the original binary form.
Inventors
- 👤 John S Whiting
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 07:32
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4917; H04L25/4923; H04L25/4925; G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/1423; G11B20/1426; G11B20/1488; G11B20/1492; H04L13/00; H04L13/02; H04L13/08
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
197 words
A system for decoding ternary data constituted of ternary words each having a plurality of terts having positive, negative and zero levels, into corresponding binary data constituted of binary words, each of said binary words having a plurality of bits, each of said plurality of binary bits corresponding to different terts of said ternary words, said system comprising a. means for converting each of said ternary words into a binary coded ternary word having a plurality of pairs of bits, each of said pairs of bits corresponding to a different tert of said ternary word, and said converting means comprising a multistage register having storage for the bits which make up a ternary word in binary coded ternary form, b. a plurality of logic means each for a different one of the bits which constitute each of said binary words, and each logic means of said plurality of logic means being responsive to a different combination of bits of said binary coded ternary words for providing the bits of said binary words corresponding to said ternary words, each of said plurality of logic means having a separate plurality of gates interconnected to different stages of said register.
Claim 2
Independent Claim
197 words
A system for decoding ternary data constituted of ternary words each having a plurality of terts having positive, negative and zero levels, into corresponding binary data constituted of binary words, each of said binary words having a plurality of bits, each of said plurality of binary bits corresponding to different terts of said ternary words, said system comprising a. means for converting each of said ternary words into a binary coded ternary word having a plurality of pairs of bits, each of said pairs of bits corresponding to a different tert of said ternary word, and said converting means comprising a multistage register having storage for the bits which make up a ternary word in binary coded ternary form, b. a plurality of logic means each for a different one of the bits which constitute each of said binary words, and each logic means of said plurality of logic means being responsive to a different combination of bits of said binary coded ternary words for providing the bits of said binary words corresponding to said ternary words, each of said plurality of logic means having a separate plurality of gates interconnected to different stages of said register.
Claim 3
Dependent Claim
108 words
The invention as set forth in claim 1 wherein said register comprises a pair of registers, each having a plurality of stages, the stages of one of said pair of registers being conditioned in one state in response to positive terts and the stages of the other of said pair of registers being conditioned to said one state in response to negative terts, corresponding stages in said one and other of said pair of registers being conditioned to the same state in response to zero level terts, and wherein said gates in each of said logic means is responsive to the states of different combinations of said registers.
Claim 4
Dependent Claim
83 words
The invention as set forth in claim 2 wherein said ternary words each have a different combination of terts and each of said ternary words corresponds to a binary word having a different combination of bits, and wherein the plurality of gates in each of said logic means is interconnected to provide an output in each case where the bit of said binary word which it provides has the same value irrespective of the values of the other bits of said binary words.
Claim 5
Dependent Claim
200 words
The invention as set forth in claim 3 wherein a. said binary words each have four bits and said corresponding ternary words each have four terts so as to provide sixteen different corresponding binary and ternary words, b. the first and last of said binary words having the bits ''''0'''' ''''0'''' ''''0'''' ''''0'''' and ''''1'''' ''''1'''' ''''1'''' ''''1'''' respectively, corresponding respectively to special ternary words, c. the remaining 14 of said binary words being represented by different ternary words having combinations of terts selected in accordance with a predetermined code, and d. the gates of said logic means each solve the following Boolean equations: A (a2 + d1 + a1 a2 b2 b2 + X) Y B (a1 + b2 c2 b1 b2 + X) Y C (b1 + d2 + d1 d2 a2 + X) Y D (c1 + d2 + d1 d2 a2 + X) Y wherein i A, B, C and D represent the bits of each of said binary words, ii. a1 a2 b1 b2 c1 c2 d1 d2 represent the terts of said ternary code in binary coded ternary form iii. X represents said first binary word, and iv. Y represents said last binary word.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-03-28 | 1975-09-27 | 1976-03-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-03-28 | 1979-09-27 | 1980-03-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-03-28 | 1983-09-27 | 1984-03-28 | $7700.00 | Window Closed / Lapsed |