US3652997A
Expired / Lapsed
US
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Control system for multiple signal channels
Assignee: Individual
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Filing: 1970-02-25
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Granted: 1972-03-28
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Expires: 1990-02-25
Abstract
Abstract A digital data processing system for controlling the sampling of data from, or the distribution of data to, a plurality of information channels is disclosed. The processing system includes a memory which serves to store a plurality of multibit binary syllables. Each of these multibit binary syllables includes a predetermined number of ones and zeros which define a sampling rate and a phase. The most significant bit appearing as a one defines the sampling rate, while all of the lesser significant bit positions, relative to the most significant bit appearing as a one, define the phase. A comparison circuit is employed to compare the contents of a digital counter, which is advanced at a predetermined rate, with each of the multibit binary syllables. Each valid comparison results in the generation of a sample signal by the comparison circuit, which sample signal enables the data available over a predetermined input information channel to be retrieved, extracted or otherwise sampled.
Inventors
- 👤 Ralph G Cromleigh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:07
CPC Classifications
H; H04; H04L; H04L5/00; H04L5/22; H04L5/24; H04L5/245; G; G06; G06F; G06F13/00; G06F13/38; G06F13/382; G06F13/385; G06F7/00; G06F7/60; G06F7/68; H04J; H04J3/00; H04J3/16; H04J3/1605; H04J3/1623; H04J3/1647
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
111 words
A data processing system for controlling the rate and time at which data is sampled from or distributed to a plurality of information channels, said system comprising: a memory for storing multibit words including a pHase/rate syllable, each of said multibit words being associated with a particular one of said information channels; a multibit sequence counter for providing a succession of uniformly increasing multibit numbers; and a comparison circuit, operatively connected to said memory and to said counter, for comparing a varying predefined number of least significant bits of each of said phase/rate syllables with a corresponding number of at least significant bits of each successive multibit number in said counter.
Claim 2
Dependent Claim
111 words
A data processing system for controlling the rate and time at which data is sampled from or distributed to a plurality of information channels, said system comprising: a memory for storing multibit words including a pHase/rate syllable, each of said multibit words being associated with a particular one of said information channels; a multibit sequence counter for providing a succession of uniformly increasing multibit numbers; and a comparison circuit, operatively connected to said memory and to said counter, for comparing a varying predefined number of least significant bits of each of said phase/rate syllables with a corresponding number of at least significant bits of each successive multibit number in said counter.
Claim 3
Dependent Claim
67 words
The apparatus defined by claim 1 further including a memory counter for applying stepping pulses to said multibit sequence counter and the contents of said memory counter to said memory, whereby the contents of said memory counter is sequentially applied to said memory at a rate allowing every multibit word to be successively read from said memory for each increase of the number in said multibit counter.
Claim 4
Dependent Claim
32 words
The apparatus defined by claim 1 wherein said multibit words further include address syllables, said apparatus further including a transfer gate to which said address syllables are successively applied from said memory.
Claim 5
Dependent Claim
43 words
The apparatus defined by claim 1 wherein said comparison circuit provides a sample pulse in response to each favorable comparison of said least significant bits of said phase/rate syllables with said least significant bits of said multibit numbers in said multibit sequence counter.
Claim 6
Dependent Claim
80 words
The apparatus defined by claim 4 wherein said multibit words further include address syllables, said apparatus further including: a channel selection circuit, operatively coupled to said information channels, for selectively enabling said data to be sampled from, or distributed to, said information channels; and transfer gating means, operatively coupled to said comparison circuit, for selectively transfering a particular one of said address syllables from said memory to said channel selection circuit in response to the application of said sample pulse.
Claim 7
Dependent Claim
98 words
The apparatus defined by claim 1 wherein said comparison circuit comprises: a comparator for comparing sets of bits applied thereto from said memory and said counter; counter gating means for selectively applying a varying predetermined number of said least significant bits of said multibit numbers in said counter to said comparator; and decoder means for detecting and applying said predefined number of least significant bits of said phase/rate syllables to said comparator and for controlling said counter gating means to apply the same number of least significant bits of said multibit numbers in said counter to said comparator.
Claim 8
Dependent Claim
133 words
The apparatus defined by claim 1 wherein said phase/rate syllables each include a plurality of bits among which the most significant bit appearing as a one designates all less significant bits for application to said comparison circuit, said comparison circuit including: a comparator for generating a sample pulse in response to a valid comparison of phase/rate bits and counter number bits applied thereto; decoder means for detecting said most significant bit appearing as a one and applying all lesser significant bits of said phase/rate syllables to said comparator; and counter gating means for applying to said comparator from said counter a number of least significant bits of said multibit number equal to the number of lesser significant bits of said phase/rate syllable applied by said decoder means from said memory to said comparator.
Claim 9
Dependent Claim
80 words
The apparatus defined by claim 7 wherein said multibit words further include address syllables, said apparatus further including: a channel selection circuit, operatively coupled to said information channels, for selectively allowing said data to be sampled from, or distributed to, said information channels; and transfer gating means, operatively coupled to said comparator, for selectively transferring a particular one of said address syllables from said Memory to said channel selection circuit in response to a sample pulse generated by said comparator.
Claim 10
Dependent Claim
81 words
The apparatus defined by claim 8 further including a memory counter for applying stepping pulses to said multibit sequence counter and the contents of said memory counter to said memory, whereby the contents of said memory counter is sequentially applied to said memory at a rate allowing every phase/rate syllable to be successively applied to said comparator and associated address syllables to be successively applied to said transfer gating means, for each increase of the number in said multibit sequence counter.
Claim 11
Dependent Claim
127 words
A data processing system for defining the rates and times at which data is applied over, or sampled from, particular information channels included in a multichannel system by providing control signals, said data processing system comprising: memory means for storing multibit words defining the rate and times at which said control signals are provided; sequencing means for cyclically providing a succession of different multibit numbers; and comparison means, operatively connected to said memory means for comparing a predetermined portion of each of said different multibit numbers with a predetermined portion of every multibit word defining the rate and times at which said control signals are provided and for providing a control signal whenever compared predetermined portions of said different multibit number and said multibit words are identical.
Claim 12
Dependent Claim
127 words
A data processing system for defining the rates and times at which data is applied over, or sampled from, particular information channels included in a multichannel system by providing control signals, said data processing system comprising: memory means for storing multibit words defining the rate and times at which said control signals are provided; sequencing means for cyclically providing a succession of different multibit numbers; and comparison means, operatively connected to said memory means for comparing a predetermined portion of each of said different multibit numbers with a predetermined portion of every multibit word defining the rate and times at which said control signals are provided and for providing a control signal whenever compared predetermined portions of said different multibit number and said multibit words are identical.
Claim 13
Dependent Claim
179 words
The apparatus according to claim 10 wherein said multibit words stored in said memory means each include a predetermined number of bits arranged in positions having an increasing or decreasing gradient of significance, each bit having a high level or a low level, the high level bit occupying the most significant position serving to define the rate at which said control signals are provided and all bits occupying lesser significant positions than said high level bit serving to define the times at which said control signals are provided, said comparison means comprising: a comparator for providing said control signals whenever the bits compared thereby are identical; decoder means for receiving said multibit words from said memory means and for applying to said comparator only those bits, of said multibit words, occupying said lesser significant positions; and gating means for receiving said different multibit numbers from said sequencing means and for applying to said comparator only those bits, of said different multibit numbers, occupying positions corresponding in significance to said lesser significant positions occupied by said bits of multibit words.
Claim 14
Dependent Claim
24 words
The apparatus according to claim 11 further including means for providing address signals corresponding to the respective information channels included in a multichannel system.
Claim 15
Dependent Claim
57 words
The apparatus according to claim 12 further including: selection means, responsive to said address signals, for applying enabling signals to said particular information channels to enable the distribution of data thereto or the sampling of data therefrom; and transfer means, responsive to said control signals, for enabling said address signals to be applied to said selection means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-03-28 | 1975-09-27 | 1976-03-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-03-28 | 1979-09-27 | 1980-03-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-03-28 | 1983-09-27 | 1984-03-28 | $7700.00 | Window Closed / Lapsed |