← Back to Patent Explorer
US3651433A Expired / Lapsed US ⏱️ 0.0 years remaining

Circuit for processing reflected signals

Assignee: Symbionics Inc
•
Filing: 1970-03-02
•
Granted: 1972-03-21
•
Expires: 1990-03-02
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A circuit for processing reflected signals is described. The reflected signal is delayed for a period of time which is equal to the period of the first half cycle of the reflected signal. It is also attenuated by an amount equal to the difference in amplitude between the first and second half cycles of the reflected signal. The delayed and attenuated signal is then combined with the reflected signal so that only the first half cycle of the reflected signal and the last half cycle of delayed signal remain.

Inventors

  • 👤 Lawrence W Langley

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 07:39
CPC Classifications
G; G01; G01S; G01S7/00; G01S7/02; G01S7/28; G01S7/285; G01S7/32; H; H03; H03K; H03K5/00; H03K5/159

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 98 words
A circuit for processing a signal to produce an output which is a substantially unchanged portion of said signal comprising: an input terminal for receiving said signal; delay means for delaying said received signal by a time period which is less than the total time period of said signal; attenuation means for attenuating said delayed signal by a predetermined amount; summation means for algebraically summing said received signal and the output of said attenuation means so that the output of said processing circuit presents a pulse which is substantially identical to a first portion of said received signal.
Claim 2
Dependent Claim 98 words
A circuit for processing a signal to produce an output which is a substantially unchanged portion of said signal comprising: an input terminal for receiving said signal; delay means for delaying said received signal by a time period which is less than the total time period of said signal; attenuation means for attenuating said delayed signal by a predetermined amount; summation means for algebraically summing said received signal and the output of said attenuation means so that the output of said processing circuit presents a pulse which is substantially identical to a first portion of said received signal.
Claim 3
Dependent Claim 18 words
The circuit of claim 1 wherein said first portion is the first one-half cycle of said received signal.
Claim 4
Dependent Claim 30 words
The circuit of claim 1 wherein said predetermined amount is equal to the difference in amplitude of the first one-half cycle and the second one-half cycle of said received signal.
Claim 5
Dependent Claim 22 words
The circuit of claim 1 wherein said delay period is the time period of the first one-half cycle of said received signal.
Claim 6
Dependent Claim 52 words
The circuit of claim 2 wherein said predetermined amount of attenuation is equal to the increment of amplitude decay naturally suffered by said received signal between its first and second one-half cycles; and wherein said delay period is equal to the time period of said first one-half cycle of said received signal.
Claim 7
Dependent Claim 100 words
The circuit of claim 1 wherein the first and second one-half cycles of said received signal are of opposite polarity; said delay means delays said received signal by a time equal to the time period of said first one-half cycle; said attenuation means attenuates said first one-half cycle by an amount required to make its amplitude equal to the amplitude of said second one-half cycle; said summation means algebraically adds said received signal and output of said attenuation means so that the preceding one-half cycle of the delayed and attenuated signal cancels the succeeding one-half cycle of the received signal.

References Cited (Backward Citations)

US2922965A Cited
US2987683A Cited
US3315171A Cited
US3482190A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1975-03-21 1975-09-20 1976-03-21 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1979-03-21 1979-09-20 1980-03-21 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1983-03-21 1983-09-20 1984-03-21 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag