Sinusoidal and square wave oscillator with automatic gain control

Claim 2

An integrated circuit comprising: biasing means for establishing a predetermined bias voltage; a solid state oscillator including a circuit loop in which an oscillating electrical signal is established when the active elements of said oscillator are biased into conduction by the application of said bias voltage; means responsive to the time averaged amplitude of positive excursions of said oscillating signal for controlling the current drawn by said oscillator such that the gain of said loop remains at unity; and means responsive to said oscillating signal for generating a clipped square wave signal, whereby the amplitudes of said oscillating and square wave signals are constant and said signals are of high spectral purity.

Claim 3

The circuit as recited in claim 1 wherein said square wave signal is generated at a level lower than a reference potential and wherein said oscillating signal is dropped in amplitude by an amount sufficient to enable generation of said square wave signal at said lower level.

Claim 4

The circuit as recited in claim 1 wherein said oscillating signal is coupled directly to said current controlling means and to said square wave generating means, and further including level translating means shared by both said current controlling and square wave generator means for removing a portion of the bias voltage normally occurring in said oscillating signal from the mean value of said oscillating signal thereby leaving a level translated signal.

Claim 5

The circuit as recited in claim 3 wherein both said current controlling and square wave generating means include half wave rectifying means to remove the remaining portion of said bias voltage from saiD oscillating signal and to provide a signal corresponding to only positive excursions of said oscillating signal.

Claim 6

The circuit as recited in claim 4 wherein said current controlling means also includes a peak following means to generate a signal corresponding to the integration of the positive excursions of said level translated signal over time, the signal produced by said integration being used to regulate the flow of current in said oscillator.

Claim 13

An integrated circuit including a pair of terminals across which bias voltage is supplied, and including a source of reference potential comprising: an oscillator including a tank circuit and first and second transistors with the emitters thereof interconnected, the first of said transistors having a collector coupled to said reference potential and the base member of said first transistor and the collector of said second transistor being connected to one end of said tank circuit so as to form a circuit loop in which an oscillating electrical signal is established, the base of said second transistor being coupled to the other end of said tank circuit and to said one of said terminals such that the base of said first transistor is provided with said bias voltage through said tank circuit; and automatic gain coNtrol means for coupling the emitters of said first and second transistors to the other of said terminals such that the current drawn by said first and second transistors is altered to regulate the gain of said loop to equal unity in response to the amplitude of the signal in said loop, said automatic gain control means being directly coupled to said circuit loop and to said emitters.

Claim 14

An integrated circuit including a pair of terminals across which bias voltage is supplied, and including a source of reference potential comprising: an oscillator including a tank circuit and first and second transistors with the emitters thereof interconnected, the first of said transistors having a collector coupled to said reference potential and the base member of said first transistor and the collector of said second transistor being connected to one end of said tank circuit so as to form a circuit loop in which an oscillating electrical signal is established, the base of said second transistor being coupled to the other end of said tank circuit and to said one of said terminals such that the base of said first transistor is provided with said bias voltage through said tank circuit; and automatic gain coNtrol means for coupling the emitters of said first and second transistors to the other of said terminals such that the current drawn by said first and second transistors is altered to regulate the gain of said loop to equal unity in response to the amplitude of the signal in said loop, said automatic gain control means being directly coupled to said circuit loop and to said emitters.

Claim 15

The integrated circuit as in recited claim 9 wherein said automatic gain control means includes: a third transistor having a collector connected to the emitters of said first and second transistors and an emitter coupled to said other terminal; a fourth transistor having a collector coupled to said reference potential, a base coupled to the base of said first transistor, said fourth transistor being biased so that it is in its conducting mode such that said fourth transistor acts as a level translator because of its base to emitter voltage drop and removes a portion of the bias voltage contained in said oscillating electrical signal from the signal appearing at the emitter thereof; a fifth transistor having its base connected to the emitter of said fourth transistor and its collector connected to the base of said third transistor such that another portion of said bias voltage is removed from said oscillating electrical signal because of the base to emitter voltage drop of said fifth transistor; a first resistive element coupled at one end to the collector of said fifth transistor and at the other end thereof to said reference potential; a second resistive element connected between the emitter of said fifth transistor and said other terminal, said first and second resistive elements biasing said fifth transistor into conduction during only excursions of the electrical signal delivered to the base thereof exceeding the voltage at said other terminal by an amount equal to the base to emitter voltage drop of said fifth transistor such that the signal at the collector of said fifth transistor is a half-wave rectified replica of said oscillating signal with no DC bias components; and a capacitative element and a third resistive element coupled in parallel between the base of said third transistor and said other terminal whereby the average voltage for said half-wave rectified replica is developed between the base of said third transistor and said other terminal such that the current through said third transistor is regulated by the peak to peak voltage in said circuit loop to limit the gain of said loop to unity, whereby the signal in said loop has a sinusoidal waveform having the frequency of said tank circuit and a constant amplitude.

Claim 16

The integrated circuit as recited in claim 10 wherein equilibrium and thus a loop gain of 1 is obtained whenever the current through said first resistive element is equal to the average current through said third transistor plus the current through said third resistive element.

Claim 17

The integrated circuit as recited in claim 11 and further including a half-wave rectifying and clipping circuit having its input directly coupled to the emitter of said fourth transistor, whereby the level translated output of said fourth transistor forms the input of said half-wave rectifying and clipping circuit and permits the production of a square wave signal below said reference potential at the output of said half-wave rectifying and clipping circuit.

Claim 18

The integrated circuit as recited in claim 12 wherein said half-wave rectifying and clipping circuit includes: a sixth transistor having a base connected to the emitter of said fourth transistor; a fourth resistive element coupled between the emitter of said sixth transistor and said other terminal and a fifth resistive element coupled between said reference potential and the collector of said sixth transistor, the ratio of the resistances of said fourth and fifth resistive elements providing said sixth transistor with a high gain and serving to bias said sixTh transistor into conduction only during positive excursions of the electrical signal delivered to the base of said sixth transistor exceeding the base to emitter voltage drop of said sixth transistor; a seventh transistor having a collector coupled to said reference potential and its base connected to the collector of said sixth transistor; and a sixth resistive element coupled between the emitter of said seventh transistor and said other terminal and having a resistance such that said seventh transistor is rendered highly conductive only when said sixth transistor is conducting, whereby a clipped square wave signal is available at the emitter of said seventh transistor at a level below said reference potential.