Packaging structure for high-frequency semiconductor devices

Claim 2

A semiconductor device package for a semiconductor wafer having active regions formed therein comprising: a. a metal header having a cavity therein defined by spaced upwardly depending sidewalls; b. a metallized thermally conducting ceramic member having first and second metal layers disposed thereon secured to said metal header within said cavity, said ceramic member being in thermal contact with the cavity portion of said metal header and said first metal layer being secured to the semiconductor wafer and an active region thereof; c. an electrical connecting member connected between aligned portions of the sidewalls of said metal header; and d. contact means for making electrical contact connected between respective ones of the active regions of the semiconductor wafer and said second metal layer and said electrical connecting member respectively.

Claim 3

A semiconductor device package as in claim 1 wherein said semiconductor wafer is a transistor chip.

Claim 4

A semiconductor device package as in claim 2 wherein the base region of the transistor chip is connected to said electrical connecting member.

Claim 5

A semiconductor device package as in claim 1 wherein said metallized thermally conducting ceramic member is fabricated of BeO.

Claim 6

A semiconductor device package as in claim 1 wherein said metal header is fabricated of oxygen-free, high-conductivity copper.

Claim 7

A semiconductor device package for a semiconductor chip having at least three active regions disposed therein comprising: a. a metal header having a cavity disposed therein defined by spaced, upwardly depending walls, each wall having integral inner and outer portions, the outer portion projecting upwardly beyond the inner portion forming plateaus upon the inner portions; b. a metallized thermally conducting ceramic member having a top and bottom surface and adapted to be received by said cavity, and having first and second metal layers disposed on the top surface thereof, a first portion of said first metal layer being connected to the semiconductor chip and the first active region thereof, the bottom surface of said ceramic member being secured to said metal header within said cavity and beIng in thermal contact therewith; c. first and second planar contact leads affixed to a second portion of said first metal layer and to said second metal layer respectively whereby said leads are adapted to be connected to active regions of the semiconductor chip; d. an electrical connecting contact member, the ends thereof each being secured to a plateau of the inner portion of each of said walls substantially above the semiconductor chip; and e. contact means for making electrical contact connected between the second and third active regions of the semiconductor chip and the electrical connecting contact member and the second contact lead respectively.

Claim 8

A semiconductor device package for a semiconductor chip having at least three active regions disposed therein comprising: a. a metal header having a cavity disposed therein defined by spaced, upwardly depending walls, each wall having integral inner and outer portions, the outer portion projecting upwardly beyond the inner portion forming plateaus upon the inner portions; b. a metallized thermally conducting ceramic member having a top and bottom surface and adapted to be received by said cavity, and having first and second metal layers disposed on the top surface thereof, a first portion of said first metal layer being connected to the semiconductor chip and the first active region thereof, the bottom surface of said ceramic member being secured to said metal header within said cavity and beIng in thermal contact therewith; c. first and second planar contact leads affixed to a second portion of said first metal layer and to said second metal layer respectively whereby said leads are adapted to be connected to active regions of the semiconductor chip; d. an electrical connecting contact member, the ends thereof each being secured to a plateau of the inner portion of each of said walls substantially above the semiconductor chip; and e. contact means for making electrical contact connected between the second and third active regions of the semiconductor chip and the electrical connecting contact member and the second contact lead respectively.

Claim 9

A semiconductor device package as in claim 6 wherein said metallized thermally conducting ceramic member is fabricated of BeO.

Claim 10

A semiconductor device package as in claim 6 wherein said metal header is fabricated of oxygen-free high-conductivity copper.

Claim 11

A semiconductor device package as in claim 6 wherein said semiconductor chip is a transistor chip.

Claim 12

A semiconductor device package as in claim 9 wherein the base region of the transistor chip is connected to said electrical connecting contact member.

Claim 13

A semiconductor device package for use with a semiconductor chip having at least three cooperating active regions therein comprising: a. a substantially oxygen-free copper header having a top surface with a cavity therein defined by upwardly depending walls in parallel spaced relation with each other, said walls having integral inner and outer portions, the inner portions being adjacent said cavity and having an upper surface substantially parallel to said cavity, the outer portion projecting upwardly beyond the upper surface of said inner portion; b. a metallized thermally conducting ceramic member having a top and bottom surface and adapted to be received within said cavity and having first and second metal layers disposed on the top surface thereof and having a first portion of said first metal layer being connected to the semiconductor chip and the first active region thereof, the bottom surface of said ceramic member being secured to said metal header within said cavity and being in thermal contact therewith; c. first and second coplanar contact leads affixed to a second portion of said first metal layer and to said second metal layer respectively whereby each of said leads is adapted to be connected to a different active region of the semiconductor chip; d. an electrical connecting contact member, each of the ends thereof being connected to the upper surface of an inner portion of each wall and being aligned substantially above the semiconductor chip; and e. contact wires connected between each of two remaining active regions of the semiconductor chip and said electrical connecting contact member and said second contact lead respectively.

Claim 14

A semiconductor device package for use with a semiconductor chip having at least three cooperating active regions therein comprising: a. a substantially oxygen-free copper header having a top surface with a cavity therein defined by upwardly depending walls in parallel spaced relation with each other, said walls having integral inner and outer portions, the inner portions being adjacent said cavity and having an upper surface substantially parallel to said cavity, the outer portion projecting upwardly beyond the upper surface of said inner portion; b. a metallized thermally conducting ceramic member having a top and bottom surface and adapted to be received within said cavity and having first and second metal layers disposed on the top surface thereof and having a first portion of said first metal layer being connected to the semiconductor chip and the first active region thereof, the bottom surface of said ceramic member being secured to said metal header within said cavity and being in thermal contact therewith; c. first and second coplanar contact leads affixed to a second portion of said first metal layer and to said second metal layer respectively whereby each of said leads is adapted to be connected to a different active region of the semiconductor chip; d. an electrical connecting contact member, each of the ends thereof being connected to the upper surface of an inner portion of each wall and being aligned substantially above the semiconductor chip; and e. contact wires connected between each of two remaining active regions of the semiconductor chip and said electrical connecting contact member and said second contact lead respectively.