Bcd to binary converter

Claim 2

A high speed binary coded decimal to binary converter, comprising: means for providing binary coded decimal signals bi3, bi2, bi1 and bi0 corresponding to each digit of a decimal number, where i is the decimal order of each digit and 0 to 3 are the decimal orders of each binary, adding means connected to the binary coded decimal signal means for adding the binary coded decimal signals in accordance with the following equation after the 10 multipliers are converted to binary form:

Claim 3

A converter of the kind described in claim 1 in which the binary coded decimal signal means includes means for setting the decimal number, and means connected to the setting means for converting each digit in the decimal number to binary coded decimal signals.

Claim 4

A converter of the kind described in claim 1 in which the output means includes a register, connected to the adding means, for storing the binary number and providing the binary signal corresponding to the stored binary number.

Claim 5

A binary coded decimal to binary converter comprising: means for providing binary coded decimal signals bi3, bi2, bi1 and bi0 corresponding to each digit of a decimal number, adding means connected to the binary coded decimal signal means for adding the binary coded decimal signals in accordance with the decimal order i of each digit and providing outputs corresponding thereto, output means connected to the adding means for providing a binary signal corresponding to the decimal number in accordance with the outputs from the adding means, the adding means including means for applying a binary coded decimal signal b00 from the binary coded decimal signal means to the output means as a binary signal corresponding to 20 and including a plurality of serially connected adders connecting the binary coded decimal signal means to the output means and in which a first adder adds signals b01 and b10 to provide a binary carry signal and a binary signal corresponding to 21, a second adder adds signals b02, b11 and b20 and the carry signal from the first adder to provide a binary carry signal and a binary signal corresponding to 22, a third adder adds signals b03, b10, b12 and b21 and the carry signal from the second adder to provide a binary carry signal and a binary signal corresponding to 23, a fourth adder adds signals b11, b13 and b22 and the carry signal from the third adder to provide a carry signal and a binary signal corresponding to 24, a fifth adder adds signaLs b12, b20 and b23 and the carry signal from the fourth adder to provide a binary carry signal and a binary signal corresponding to 25, a sixth adder adds signals b13, b20 and b21 and the carry signal from the fifth adder to provide a binary carry signal and a binary signal corresponding to 26, a seventh adder adds signals b21 and b22 and the carry signal from the sixth adder to provide a binary carry signal and a binary signal corresponding to 27, and an eighth adder adds signals b22 and b23 and the carry signal from the seventh adder to provide a binary carry signal and a binary signal corresponding to 28, and a ninth adder adds signal b23 and the carry signal from the eighth adder to provide a signal corresponding to 29.

Claim 6

A binary coded decimal to binary converter comprising: means for providing binary coded decimal signals bi3, bi2, bi1 and bi0 corresponding to each digit of a decimal number, adding means connected to the binary coded decimal signal means for adding the binary coded decimal signals in accordance with the decimal order i of each digit and providing outputs corresponding thereto, output means connected to the adding means for providing a binary signal corresponding to the decimal number in accordance with the outputs from the adding means, the adding means including means for applying a binary coded decimal signal b00 from the binary coded decimal signal means to the output means as a binary signal corresponding to 20 and including a plurality of serially connected adders connecting the binary coded decimal signal means to the output means and in which a first adder adds signals b01 and b10 to provide a binary carry signal and a binary signal corresponding to 21, a second adder adds signals b02, b11 and b20 and the carry signal from the first adder to provide a binary carry signal and a binary signal corresponding to 22, a third adder adds signals b03, b10, b12 and b21 and the carry signal from the second adder to provide a binary carry signal and a binary signal corresponding to 23, a fourth adder adds signals b11, b13 and b22 and the carry signal from the third adder to provide a carry signal and a binary signal corresponding to 24, a fifth adder adds signaLs b12, b20 and b23 and the carry signal from the fourth adder to provide a binary carry signal and a binary signal corresponding to 25, a sixth adder adds signals b13, b20 and b21 and the carry signal from the fifth adder to provide a binary carry signal and a binary signal corresponding to 26, a seventh adder adds signals b21 and b22 and the carry signal from the sixth adder to provide a binary carry signal and a binary signal corresponding to 27, and an eighth adder adds signals b22 and b23 and the carry signal from the seventh adder to provide a binary carry signal and a binary signal corresponding to 28, and a ninth adder adds signal b23 and the carry signal from the eighth adder to provide a signal corresponding to 29.

Claim 7

A converter of the kind described in claim 4 in which the first adder is a first full adder, the second adder includes second and third full adders connected to the binary coded decimal signal means, and to each other, the third full adder being also connected to output means; the third adder includes fourth, fifth and sixth full adders connected to the binary coded decimal signal means and the fifth full adder also connects the fourth full adder to the sixth full adder which is also connected to the output means; the fourth adder includes seventh and eighth full adders connected to the binary coded decimal signal means and the eighth full adder is also connected to the output means, and a first half adder connecting the seventh and eighth full adders; the fifth adder includes a ninth full adder and a second half adder connected to the binary coded decimal signal means, a 10th full adder connected to the ninth full adder and to the output means and a third half adder connecting the second half adder to the 10th full adder; the sixth adder includes an 11th full adder and a fourth half adder connected to the binary coded decimal signal means, a 12th full adder connected to the 11th full adder and to the output means, and a fifth half adder connecting the fourth half adder to the 12th full adder; the seventh adder includes a 13th full adder connected to the connecting means and a sixth half adder connecting the 13th full adder to the output means; the eighth adder includes a 14th full adder connected to the binary coded decimal signal means and a seventh half adder connecting the 14th full adder to the output means; and the ninth adder includes an eighth half adder connected to the binary coded decimal signal means and a ninth half adder connecting the eighth half adder to the output means.