Digital measuring system

Claim 2

In a process for digital measurement of a value with respect to an object comprising the steps of: A. generating two series of pulse signals indicative of said value by means of a pair of detecting stations moved from the respective reference points thereof until they reach predetermined points set with respect to the object, and B. counting said two series of pulse signals by means of a counting means having a minimal sequential response interval so as to obtain the value to be measured with respect to the object, the improvement comprising the steps of: C. converting said two series of pulse signals respectively into two series of rectangular pulses, the pulses in each of said two series of rectangular pulses having a predetermined duration greater than said minimal sequential response interval of said counting means, D. producing a first logic OR combination output and a logic NAND combination output from said two series of rectangular pulses, E. respectively differentiating said first logic OR combination output and said logic NAND combination output to produce respectively two series of instantaneous output pulses in which the time interval between any two respectively adjacent pulses occurring in said two series of instantaneous output pulses is made at least equal to said predetermined duration of said rectangular pulses, F. producing a second logic OR combination output from said two series of instantaneous output pulses, and G. counting said second logic OR combination output derived from said two series of instantaneous output pulses by means of said counting means, thereby preventing the type of faulty counter operation in which first and second pulses occur sequentially so fast that the counter cannot respond separately to the second pulse.

Claim 3

A process according to claim 1, further comprising the steps of: A. generating an additional series of pulse signals indicative of an amount of compensation to be provided for the measured value, B. summing said second logic OR combination output and said additional series of pulse signals to generate compensation output pulses, and C. counting said compensation output pulses by said counting means, thereby simultaneously counting said second OR combination output and said compensation output.

Claim 4

In a process for digital measurement of a value with respect to an object comprising the steps of: A. Generating two series of pulse signals indicative of said value by means of a pair of detecting stations moved from the respective reference points thereof until they reach predetermined points with respect to the object, and B. counting said two series of pulse signals by means of a counting means having a minimal sequential response interval so as to obtain the value to be measured with respect to the object, the improvement comprising the steps of: C. converting said two series of pulse signals respectively into two series of rectangular pulses, the pulses in each of said two series of rectangular pulses having an approximately predetermined duration greater than said minimal sequential response interval of said counting means, D. producing a logic NOR combination output and a logic AND combination output from said two series of rectangular pulses, E. respectively differentiating said logic NOR combination output and said logic AND combination output to produce respectively two series of instantaneous output pulses in which the time interval between any two respectively adjacent pulses occurring in said two series of instantaneous output pulses is made at least equal to said predetermined duration of said rectangular pulses, F. producing a logic OR combination output from said two series of instantaneous output pulses, and G. counting said logic OR combination output derived fRom said two series of instantaneous output pulses by means of said counting means, thereby preventing the type of faulty counter operation in which first and second pulses occur sequentially so fast that the counter cannot respond separately to the second pulse.

Claim 5

In a process for digital measurement of a value with respect to an object comprising the steps of: A. Generating two series of pulse signals indicative of said value by means of a pair of detecting stations moved from the respective reference points thereof until they reach predetermined points with respect to the object, and B. counting said two series of pulse signals by means of a counting means having a minimal sequential response interval so as to obtain the value to be measured with respect to the object, the improvement comprising the steps of: C. converting said two series of pulse signals respectively into two series of rectangular pulses, the pulses in each of said two series of rectangular pulses having an approximately predetermined duration greater than said minimal sequential response interval of said counting means, D. producing a logic NOR combination output and a logic AND combination output from said two series of rectangular pulses, E. respectively differentiating said logic NOR combination output and said logic AND combination output to produce respectively two series of instantaneous output pulses in which the time interval between any two respectively adjacent pulses occurring in said two series of instantaneous output pulses is made at least equal to said predetermined duration of said rectangular pulses, F. producing a logic OR combination output from said two series of instantaneous output pulses, and G. counting said logic OR combination output derived fRom said two series of instantaneous output pulses by means of said counting means, thereby preventing the type of faulty counter operation in which first and second pulses occur sequentially so fast that the counter cannot respond separately to the second pulse.

Claim 6

A process according to claim 3, further comprising the steps of: A. generating an additional series of pulse signals indicative of the amount of compensation to be provided for the measured value, B. Summing said logic OR combination output and said additional series of pulse signals to generate compensation output pulses, and C. counting said compensation output pulses by said counting means, thereby simultaneously counting said OR combination output and said compensation output.

Claim 7

In a process for digital measurement of a value with respect to an object comprising the steps of: A. generating a first and a second series each of addition and subtraction pulse signals indicative of said value respectively by means of a first and a second detecting station, each station being moved from a respective reference point thereof until it reaches a predetermined point with respect to the object, said addition pulse signals being generated when each of said first and second detecting stations is moved in a predetermined direction with respect to each of said detecting stations while said subtraction pulse signals are generated when each of said detecting stations is moved in the opposite direction, and B. counting said addition and subtraction pulse signals of said first and second series by means of a reversible counting means having a minimal sequential response interval to obtain the value to be measured with respect to the object, the improvement comprising the steps of: C. converting said addition and subtraction pulse signals in each of said first and second series into rectangular pulses, each of said rectangular pulses being selected to have an approximately predetermined duration greater than said minimal sequential response interval of said counting means, D. producing a first logic NOR combination output and a first logic AND combination output of said rectangular pulses derived from said addition pulse signals of said first and second series, E. producing a second logic NOR combination output and a second logic AND combination output of said rectangular pulses derived from said subtraction pulse signals of said first and second series, F. producing a third logic AND combination output of said rectangular pulses derived from said addition pulse signals of said first series and from said subtraction pulse signals of said second series, G. producing a fourth logic AND combination output of said rectangular pulses derived from said subtraction pulse signals of said first series and from said addition pulse signals of said second series, H. differentiating said first NOR and first AND combination outputs to respectively produce a first and a second series of instantaneous output pulses, wherein the time interval between said instantaneous output pulses occurring in said first and second series of instantaneous output pulses is caused to be at least said predetermined duration, I. differentiating said second NOR and said AND combination outputs to produce respectively a third and a fourth series of instantaneous output pulses, wherein the time interval between said instantaneous output pulses occurring in said third and fourth series of instantaneous output pulses is caused to be at least said predetermined duration, J. producing a first logic OR combination of said first and said second series of instantaneous output pulses, K. producing a second logic OR combination output of said third and said fourth series of instantaneous output pulses, L. producing a third logic OR combination output of said third and said fourth AND combination outputs, M. differentiating said Third logic OR combination output to produce a fifth series of instantaneous output pulses, N. converting said fifth series of instantaneous output pulses into rectangular pulses, the duration of each pulse in said fifth series being selected to be at least longer than said predetermined duration, O. producing negative pulses by inverting the rectangular pulses derived from said fifth series of instantaneous output pulses, P. producing a fifth logic AND combination output of said first logic OR combination output and said negative pulses, and Q. producing a sixth logic AND combination output of said second logic OR combination output and said negative pulses, thereby permitting said fifth logic AND combination output and said sixth logic AND combination output derived respectively from said addition pulse signals and said subtraction pulse signals to be counted by one and the same reversible counting means without the type of faulty counter operation in which two pulses occur sequentially so fast that the counter cannot respond separately to the second of the two pulses.

Claim 8

In a process for digital measurement of a value with respect to an object comprising the steps of: A. generating a first and a second series each of addition and subtraction pulse signals indicative of said value respectively by means of a first and a second detecting station, each station being moved from a respective reference point thereof until it reaches a predetermined point with respect to the object, said addition pulse signals being generated when each of said first and second detecting stations is moved in a predetermined direction with respect to each of said detecting stations while said subtraction pulse signals are generated when each of said detecting stations is moved in the opposite direction, and B. counting said addition and subtraction pulse signals of said first and second series by means of a reversible counting means having a minimal sequential response interval to obtain the value to be measured with respect to the object, the improvement comprising the steps of: C. converting said addition and subtraction pulse signals in each of said first and second series into rectangular pulses, each of said rectangular pulses being selected to have an approximately predetermined duration greater than said minimal sequential response interval of said counting means, D. producing a first logic NOR combination output and a first logic AND combination output of said rectangular pulses derived from said addition pulse signals of said first and second series, E. producing a second logic NOR combination output and a second logic AND combination output of said rectangular pulses derived from said subtraction pulse signals of said first and second series, F. producing a third logic AND combination output of said rectangular pulses derived from said addition pulse signals of said first series and from said subtraction pulse signals of said second series, G. producing a fourth logic AND combination output of said rectangular pulses derived from said subtraction pulse signals of said first series and from said addition pulse signals of said second series, H. differentiating said first NOR and first AND combination outputs to respectively produce a first and a second series of instantaneous output pulses, wherein the time interval between said instantaneous output pulses occurring in said first and second series of instantaneous output pulses is caused to be at least said predetermined duration, I. differentiating said second NOR and said AND combination outputs to produce respectively a third and a fourth series of instantaneous output pulses, wherein the time interval between said instantaneous output pulses occurring in said third and fourth series of instantaneous output pulses is caused to be at least said predetermined duration, J. producing a first logic OR combination of said first and said second series of instantaneous output pulses, K. producing a second logic OR combination output of said third and said fourth series of instantaneous output pulses, L. producing a third logic OR combination output of said third and said fourth AND combination outputs, M. differentiating said Third logic OR combination output to produce a fifth series of instantaneous output pulses, N. converting said fifth series of instantaneous output pulses into rectangular pulses, the duration of each pulse in said fifth series being selected to be at least longer than said predetermined duration, O. producing negative pulses by inverting the rectangular pulses derived from said fifth series of instantaneous output pulses, P. producing a fifth logic AND combination output of said first logic OR combination output and said negative pulses, and Q. producing a sixth logic AND combination output of said second logic OR combination output and said negative pulses, thereby permitting said fifth logic AND combination output and said sixth logic AND combination output derived respectively from said addition pulse signals and said subtraction pulse signals to be counted by one and the same reversible counting means without the type of faulty counter operation in which two pulses occur sequentially so fast that the counter cannot respond separately to the second of the two pulses.

Claim 9

In a process for digital measurement of a value with respect to an object comprising the steps of: A. generating a first and a second series each of addition and subtraction pulse signals indicative of said value respectively by means of a first and a second detecting station, each station being moved from the respective reference point thereof until it reaches a predetermined point with respect to the object, said addition pulse signals being generated when each of said first and second detecting stations is moved in a predetermined direction with respect to each of said detecting stations while said subtraction pulse signals are generated when each of said detecting stations is moved in the opposite direction, and B. counting said addition and subtraction pulse signals of said first and second series by reversible counting means having a minimal sequential response interval so as to obtain the value to be measured with respect to the object the improvement comprising the steps of: C. converting said addition and subtraction pulse signals in each of said first and second series into rectangular pulses, each of said rectangular pulses being selected to have about a predetermined duration greater than said minimal sequential response interval of said counting means, D. producing a first logic OR combination output and a first logic NAND combination output of said rectangular pulses derived from said addition pulses signals of said first and second series, E. producing a second logic OR combination output and a second logic NAND combination output of said rectangular pulses derived from said subtraction pulse signals of said first and second series, F. producing a first logic AND combination output of said rectangular pulses derived from said addition pulse signals of said first series and from said subtraction pulse signals of said second series, G. producing a second logic AND combination output of said rectangular pulses derived from said subtraction pulse signals of said first series and from said addition pulse signals of said second series, H. differentiating said first OR and said first NAND combination outputs to produce respectively a first and a second series of instantaneous output pulses, wherein the time interval of said instantaneous output pulses occurring in said first and second series is at least equal to said predetermined duration, I. differentiating said second OR and said second NAND combination outputs to produce respectively a third and a fourth series of instantaneous output pulses wherein the time interval of said instantaneous output pulses occurring in said third and fourth series is at least equal to said predetermined duration, J. producing a third logic OR combination output of said first and said second series of instantaneous output Pulses, K. producing a fourth logic OR combination output of said third and said fourth series of instantaneous output pulses, L. producing a fifth logic OR combination output of said first and second AND combination outputs, M. differentiating said fifth logic OR combination output to produce a fifth series of instantaneous output pulses, N. converting said fifth series of instantaneous output pulses into rectangular pulses, the duration of each rectangular pulse being selected to be at least longer than said predetermined duration, O. producing negative pulses by inverting said rectangular pulses derived from said fifth series of instantaneous output pulses, P. producing a third logic AND combination output of said third logic OR combination output and said negative pulses, and Q. producing a fourth logic AND combination output of said second logic OR combination output and said negative pulses, thereby permitting said third logic AND combination output and said fourth logic AND combination output, derived respectively from said addition pulse signals and said subtraction pulse signals, to be counted by one and the same counting means without the type of faulty counter operation in which two pulses occur sequentially so fast that the counter cannot respond separately to the second of the two pulses.

Claim 10

In a process for digital measurement of a value with respect to an object comprising the steps of: A. generating a first and a second series each of addition and subtraction pulse signals indicative of said value respectively by means of a first and a second detecting station, each station being moved from the respective reference point thereof until it reaches a predetermined point with respect to the object, said addition pulse signals being generated when each of said first and second detecting stations is moved in a predetermined direction with respect to each of said detecting stations while said subtraction pulse signals are generated when each of said detecting stations is moved in the opposite direction, and B. counting said addition and subtraction pulse signals of said first and second series by reversible counting means having a minimal sequential response interval so as to obtain the value to be measured with respect to the object the improvement comprising the steps of: C. converting said addition and subtraction pulse signals in each of said first and second series into rectangular pulses, each of said rectangular pulses being selected to have about a predetermined duration greater than said minimal sequential response interval of said counting means, D. producing a first logic OR combination output and a first logic NAND combination output of said rectangular pulses derived from said addition pulses signals of said first and second series, E. producing a second logic OR combination output and a second logic NAND combination output of said rectangular pulses derived from said subtraction pulse signals of said first and second series, F. producing a first logic AND combination output of said rectangular pulses derived from said addition pulse signals of said first series and from said subtraction pulse signals of said second series, G. producing a second logic AND combination output of said rectangular pulses derived from said subtraction pulse signals of said first series and from said addition pulse signals of said second series, H. differentiating said first OR and said first NAND combination outputs to produce respectively a first and a second series of instantaneous output pulses, wherein the time interval of said instantaneous output pulses occurring in said first and second series is at least equal to said predetermined duration, I. differentiating said second OR and said second NAND combination outputs to produce respectively a third and a fourth series of instantaneous output pulses wherein the time interval of said instantaneous output pulses occurring in said third and fourth series is at least equal to said predetermined duration, J. producing a third logic OR combination output of said first and said second series of instantaneous output Pulses, K. producing a fourth logic OR combination output of said third and said fourth series of instantaneous output pulses, L. producing a fifth logic OR combination output of said first and second AND combination outputs, M. differentiating said fifth logic OR combination output to produce a fifth series of instantaneous output pulses, N. converting said fifth series of instantaneous output pulses into rectangular pulses, the duration of each rectangular pulse being selected to be at least longer than said predetermined duration, O. producing negative pulses by inverting said rectangular pulses derived from said fifth series of instantaneous output pulses, P. producing a third logic AND combination output of said third logic OR combination output and said negative pulses, and Q. producing a fourth logic AND combination output of said second logic OR combination output and said negative pulses, thereby permitting said third logic AND combination output and said fourth logic AND combination output, derived respectively from said addition pulse signals and said subtraction pulse signals, to be counted by one and the same counting means without the type of faulty counter operation in which two pulses occur sequentially so fast that the counter cannot respond separately to the second of the two pulses.

Claim 11

A digital measurement apparatus comprising: A. first measurement means for generating a first train of pulses, B. Second measurement means for generating a second train of pulses, C. counter means having a minimal sequential response interval, D. means responsive to said first train of pulses for generating a corresponding first series of rectangular pulses, E. means responsive to said second train of pulses for generating a corresponding second series of rectangular pulses, each of the rectangular pulses in said first and second series being at least equal in length to said minimal sequential response interval, F. first and second logic means each having said first and said second series as inputs, one of said logic means being a gate having one type of OR function and the other of said logic means being a gate having one type of AND function, said first and said second logic means respectively producing a first and a second logic combination output signal, G. OR gate means responsive to said first and said second logic combination output signals for generating a combined pulse train for application to said counter means as a signal to be counted.

Claim 12

A digital measurement apparatus comprising: A. first measurement means for generating a first train of pulses, B. Second measurement means for generating a second train of pulses, C. counter means having a minimal sequential response interval, D. means responsive to said first train of pulses for generating a corresponding first series of rectangular pulses, E. means responsive to said second train of pulses for generating a corresponding second series of rectangular pulses, each of the rectangular pulses in said first and second series being at least equal in length to said minimal sequential response interval, F. first and second logic means each having said first and said second series as inputs, one of said logic means being a gate having one type of OR function and the other of said logic means being a gate having one type of AND function, said first and said second logic means respectively producing a first and a second logic combination output signal, G. OR gate means responsive to said first and said second logic combination output signals for generating a combined pulse train for application to said counter means as a signal to be counted.

Claim 13

An apparatus according to claim 7 wherein said one type of OR function is a noninverted OR and said one type of AND function is a NAND function.

Claim 14

An apparatus according to claim 7 wherein said one type of OR function is a NOR function and said one type of AND function is a noninverted AND.

Claim 15

An apparatus according to claim 7 wherein said OR gate means further comprises: A. an OR gate having two input terminals, B. means for differentiating said first logic combination output signal to derive a first differentiated signal for application to one of said two input terminals, and C. means for differentiating said second logic combination output signal to derive a second differentiated signal for application to the other of said two input terminals.

Claim 16

An apparatus according to claim 7 wherein said first measurement means and said second measurement means respectively comprise first and second detectors, each of said detectors comprising an elongated feeler, said detectors being mounted with their respective feelers facing each other, aligned on a common axis, and further comprising: means for moving the feelers with respect to each other to measure the distance therebetween.

Claim 17

A process for processing digital data in order to merge two input trains of pulses into a single output train of pulses while preventing any two adjacent pulses in said single output train which are respectively derived from said two input trains from occurring any closer in time to each other than a predetermined minimal sequential response interval, comprising the steps of: A. generating a first one of said two input trains in response to a first measurement operation, B. generating a second one of said two input trains in response to a second measurement operation, C. generating a first series of rectangular pulses corresponding to said first one of said two input trains, D. generating a second series of rectangular pulses corresponding to said second one of said two input trains, the rectangular pulses in said first and said second series of rectangular pulses being at least equal in length to said minimal sequential response interval, E. logically combining said first and said second series by one type of OR function to provide a first logic combination output signal, F. logically combining said first and said second series by one type of AND function to provide a second logic combination output signal, and G. logically combining said first and said second logic combination output signal by an OR function to produce said single output train of pulses.

Claim 18

A process for processing digital data in order to merge two input trains of pulses into a single output train of pulses while preventing any two adjacent pulses in said single output train which are respectively derived from said two input trains from occurring any closer in time to each other than a predetermined minimal sequential response interval, comprising the steps of: A. generating a first one of said two input trains in response to a first measurement operation, B. generating a second one of said two input trains in response to a second measurement operation, C. generating a first series of rectangular pulses corresponding to said first one of said two input trains, D. generating a second series of rectangular pulses corresponding to said second one of said two input trains, the rectangular pulses in said first and said second series of rectangular pulses being at least equal in length to said minimal sequential response interval, E. logically combining said first and said second series by one type of OR function to provide a first logic combination output signal, F. logically combining said first and said second series by one type of AND function to provide a second logic combination output signal, and G. logically combining said first and said second logic combination output signal by an OR function to produce said single output train of pulses.