US3648239A
Expired / Lapsed
US
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System for translating to and from single error correction-double error detection hamming code and byte parity code
Assignee: International Business Machines Corp
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Filing: 1970-06-30
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Granted: 1972-03-07
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Expires: 1990-06-30
Abstract
Abstract An SEC/DED error detection and data translation mechanism is described. By the use of unique circuit design features, the same logical circuitry is capable of automatically taking Hamming encoded data from memory and parity encoding same for transmission elsewhere in the system as well as forming the necessary syndromes for purposes of error detection and correction. The same circuitry is capable of receiving encoded data from elsewhere in the system, first checking for any parity error and, if parity is proper, will generate the necessary Hamming check bits for storing in the memory together with the data information. The disclosed circuitry, by means of the unique partitioning thereof, separates the error detection and correction functions. It also generates parity bits essentially in parallel with error detection after a memory read cycle with the result that the data is propagated through the correction circuitry only when a single data bit error is detected.
Inventors
- 👤 William C Carter
- 👤 Keith A Duke
- 👤 Donald C Jessep Jr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 13:33
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1012
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
259 words
A data translation circuit means for use with single error correction-double error detection Hamming coded data for examining Hamming coded data from an associated memory and placing same on a system bus in byte parity coded form and for examining byte parity coded data received from the system bus and for storing said data in said memory in single error correctingdouble error detecting Hamming coded form, said system comprising: storage means for selectively storing data bits and check bits on a memory read access and for storing data bits and byte parity bits on a memory write access, connection matrix means for selectively sampling predetermined bits in said storage means, first EXCLUSIVE OR tree circuit means connected to the output of said connection matrix means for producing special purpose bits, storage means for storing the original data bits and the special purpose bits from said first EXCLUSIVE OR tree means, second EXCLUSIVE OR tree circuit means for examining the parity across the special purpose bits and associated data byte, register means for storing the results of said second EXCLUSIVE OR tree output, wherein all said results should be of a predetermined binary state if the correct parity relationship exists across all of the data bytes and their associated special purpose bits, and means for examining the results of said second EXCLUSIVE OR tree operation and means for signaling an appropriate error when the input data is received from the system bus and for signaling a data or check bit error when the input data originated in the associated memory.
Claim 2
Dependent Claim
259 words
A data translation circuit means for use with single error correction-double error detection Hamming coded data for examining Hamming coded data from an associated memory and placing same on a system bus in byte parity coded form and for examining byte parity coded data received from the system bus and for storing said data in said memory in single error correctingdouble error detecting Hamming coded form, said system comprising: storage means for selectively storing data bits and check bits on a memory read access and for storing data bits and byte parity bits on a memory write access, connection matrix means for selectively sampling predetermined bits in said storage means, first EXCLUSIVE OR tree circuit means connected to the output of said connection matrix means for producing special purpose bits, storage means for storing the original data bits and the special purpose bits from said first EXCLUSIVE OR tree means, second EXCLUSIVE OR tree circuit means for examining the parity across the special purpose bits and associated data byte, register means for storing the results of said second EXCLUSIVE OR tree output, wherein all said results should be of a predetermined binary state if the correct parity relationship exists across all of the data bytes and their associated special purpose bits, and means for examining the results of said second EXCLUSIVE OR tree operation and means for signaling an appropriate error when the input data is received from the system bus and for signaling a data or check bit error when the input data originated in the associated memory.
Claim 3
Dependent Claim
48 words
A data translation system as set forth in claim 1 wherein the output of the second EXCLUSIVE OR tree means should be a series of binary bits of the same binary value where the proper parity relationship exists across each data byte and its associated special purpose bit.
Claim 4
Dependent Claim
60 words
A data translation system as set forth in claim 2 wherein said examining means includes means for signalling a parity error if an error is detected during a memory write access and means for signaling a memory output error and specifying a single check bit error, a single data bit error, or a double error during a memory read access.
Claim 5
Dependent Claim
60 words
A data translation system as set forth in claim 1 wherein said connection matrix and first EXCLUSIVE OR tree circuit means is operative to selectively generate byte parity bits from the data bits and Hamming code bits on a memory read access or Hamming code check bits from he data bits and byte parity bits on a memory write access.
Claim 6
Dependent Claim
75 words
A data translation system as set forth in claim 4 wherein said connection matrix comprises a plurality of cables connected to predetermined bits in said storage means, the particular connections being determined from a parity check matrix and there being as many cables as special purpose bits to be generated, wherein said generated special purpose bits comprise byte parity bits on a memory read access and Hamming code check bits on a memory write access.
Claim 7
Dependent Claim
47 words
A data translation system as set forth in claim 5 wherein said connection matrix is connected and the parity check matrix is selected so that no cable of said connection matrix is connected to the same pattern of bits in said storage means as any other cable.
Claim 8
Dependent Claim
38 words
A data translation system as set forth in claim 6 wherein said first EXCLUSIVE OR tree circuit means comprises a pluralIty of EXCLUSIVE OR circuit trees each being connected to a single output cable from said connection matrix.
Claim 9
Dependent Claim
51 words
A data translation system as set forth in claim 7 wherein said second EXCLUSIVE OR circuit tree means comprises a plurality of EXCLUSIVE OR circuit trees each connected to said storage means so that it examines all of the bits of a particular data byte and an associated special purpose bit.
Claim 10
Dependent Claim
74 words
A data translation system as set forth in claim 5 wherein said storage means comprises first and second data register means the output of the first data register means being connected to the input of said connection matrix and thence to the input of said first EXCLUSIVE OR circuit tree means and wherein the output of said second data register means is connected to the input of said second EXCLUSIVE OR circuit tree means.
Claim 11
Dependent Claim
67 words
A data translation system as set forth in claim 5 including means for gating data bytes and byte parity bits directly into both the first and second data register means on a memory write access and means for gating said data and parity bits from the second data register means through said second EXCLUSIVE OR circuit tree means for examining the byte parity of said received data.
Claim 12
Dependent Claim
81 words
A data translation system as set forth in claim 10 including means operable upon a successful parity examination to gate the data bits and parity bits received from the system bus from the first data register means through the connection matrix and the first EXCLUSIVE OR circuit tree means to generate the SEC/DED Hamming code check bits from the data bits and byte parity bits and, means for gating said data bits and generated check bits to the memory for storage.
Claim 13
Dependent Claim
102 words
A data translation system as set forth in claim 5 wherein said special purpose bits comprise byte parity bits where the input to the connection matrix and the first EXCLUSIVE OR circuit tree means comprise data bits and check bits on a memory read access, and means for changing a generated byte parity bit when the examining means detects a single check bit error from the output of the second EXCLUSIVE OR circuit tree means, the parity bit changed being the one directly connected to that portion of said second EXCLUSIVE OR circuit tree means which caused an error signal to occur.
Claim 14
Dependent Claim
92 words
A data translation system as set forth in claim 12 wherein the output of said second EXCLUSIVE OR operation comprises Hamming code syndrome bits, means for examining the number of syndrome bits in error and means responsive to said last named means for indicating a single check bit error if only one syndrome bit is in error indicating a single data bit error if an odd number of syndrome bits greater than one is in error, or for indicating a double error if an even number of syndrome bits are in error.
Claim 15
Dependent Claim
69 words
A data translation system as set forth in claim 13 including means responsive to said last-named indicating means upon a determination that a single data bit error is present to gate the data bits and syndrome bits to the correction circuit means and means for gating the data bits from the correction circuit means back to said storage means without changing the Hamming code check bits currently stored therein.
Claim 16
Dependent Claim
65 words
A data translation system as set forth in claim 14 including means for generating new byte parity bits after said data bits have been corrected and returned to said storage means from said correction circuit means, said means including means for gating said corrected data bits and said unaltered check bits previously stored therein through said connection matrix and said first EXCLUSIVE OR circuitry means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-03-07 | 1975-09-06 | 1976-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-03-07 | 1979-09-06 | 1980-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-03-07 | 1983-09-06 | 1984-03-07 | $7700.00 | Window Closed / Lapsed |