Circuit for indicating a delay time of a delayed pulse

Claim 2

A delay time indicating circuit comprising gate signal generating means having an input terminal for connection to a source of synchronizing signals, an output terminal for a gate signal initiated at each said synchronizing signal, and a feedback terminal for receiving a feedback pulse for terminating said gate signal; feedback signal generating means having a first input terminal coupled to the output terminal of said gate signal generating means, having a second input terminal for coupling to a variable DC voltage source, and having an output terminal from which is generated said feedback signal at a time delay from the start of the gate signal proportional to the amplitude of said DC voltage; pulse generator means having an input terminal connected to the output terminal of said gate signal generating means, and an output terminal from which is generated a train of pulses; selector circuit means for selecting an nth pulse of said train of pulses during the time of said gate signal, and having an input terminal connected to said output terminal of said pulse generator means, and having an output terminal from which is generated a delayed signal pulse at the time of said nth pulse; and, first delay time indicating means for generating an indicating signal initiated at the time of said delayed signal pulse and terminated at the initiation of the subsequent gate signal, said delay time indicating means having a first input terminal connected to receive said gate signal, a second input terminal connected to receive said delayed signal pulse, and an output terminal from which is generated said indicating signal, whereby said DC voltage can be varied and then measured at the time of generation of the first indicating signal, thereby permitting determination of the delay time of said nth pulse.

Claim 3

A delay time indicating circuit comprising gate signal generating means having an input terminal for connection to a source of synchronizing signals, an output terminal from which is generated a gate signal initiated at said synchronizing signal, and a feedback terminal for receiving a feedback pulse for terminating said gate signal; feedback signal generating means having a first input terminal coupled to the output terminal of said gate signal generating means, having a second input terminal for coupling to a variable DC voltage source, and including a sawtooth generator circuit for generating a sawtooth wave initiated upon reception of the leading edge of said gate signal, a pulse generating circuit having an output terminal from which is produced said feedback pulse when the amplitude of said sawtooth wave reaches a DC value at said second input terminal; pulse generator means having an input terminal connected to the output terminal of said gate signal generating means, and an output terminal from which is generated a train of pulses for the duration of each said gate signal; selector circuit means for selecting an nth pulse of said trAin of pulses, said selector circuit means having an input terminal connected to said output terminal of said pulse generator means, and having an output terminal from which is generated a delayed signal pulse at the time of said nth pulse; and, first delay time indicating means for generating an indicating signal initiated at the time of said delayed signal pulse and terminated at the initiation of the subsequent gate signal, said delay time indicating means having a first input terminal connected to receive said gate signal, a second input terminal connected to receive said delayed signal pulse, and an output terminal from which is generated said indicating signal, whereby said DC voltage can be varied and then measured at the time of generation of the first indicating signal, thereby permitting determination of the delay time of said nth pulse.

Claim 4

A delay time indicating circuit comprising gate signal generating means having an input terminal for connection to a source of synchronizing signals, an output terminal from which is generated a gate signal initiated at said synchronizing signal, and a feedback terminal for receiving a feedback pulse for terminating said gate signal; feedback signal generating means having a first input terminal coupled to the output terminal of said gate signal generating means, having a second input terminal for coupling to a variable DC voltage source, and including a sawtooth generator circuit for generating a sawtooth wave initiated upon reception of the leading edge of said gate signal, a pulse generating circuit having an output terminal from which is produced said feedback pulse when the amplitude of said sawtooth wave reaches a DC value at said second input terminal; pulse generator means having an input terminal connected to the output terminal of said gate signal generating means, and an output terminal from which is generated a train of pulses for the duration of each said gate signal; selector circuit means for selecting an nth pulse of said trAin of pulses, said selector circuit means having an input terminal connected to said output terminal of said pulse generator means, and having an output terminal from which is generated a delayed signal pulse at the time of said nth pulse; and, first delay time indicating means for generating an indicating signal initiated at the time of said delayed signal pulse and terminated at the initiation of the subsequent gate signal, said delay time indicating means having a first input terminal connected to receive said gate signal, a second input terminal connected to receive said delayed signal pulse, and an output terminal from which is generated said indicating signal, whereby said DC voltage can be varied and then measured at the time of generation of the first indicating signal, thereby permitting determination of the delay time of said nth pulse.

Claim 5

The invention as set forth in claim 2, in which said delay time indicating means comprises a flip-flop circuit having input means for causing said flip-flop to change from its original state at the time of each said delayed signal pulse, and to change back to its said original state at the time of initiation of the next succeeding gate signal.

Claim 6

The invention as set forth in claim 2, further comprising second delay time indicating means for generating a signal which is initiated at the time of said delayed signal and which is terminated at the simultaneous condition of the absence of said first delay time indicating signal and the termination of said gate signal.

Claim 7

The invention as set forth in claim 4, in which said second delay time indicating means has a first input terminal connected to receive said gate signal, a second input terminal connected to receive said first delay time indicating signal, and an output terminal form which is generated said second delay time indicating signal.

Claim 8

The invention as set forth in claim 5, in which said second delay time indicating means comprises a flip-flop circuit having input means for causing said flip-flop to change from its original state at the time of reception of said first delay time indicating signal, and to change back to its said original state at the time of termination of said gate signal during an absence of said first delay time indicating signal.

Claim 9

A delay time indicating circuit comprising means for generating a gate signal having a duration proportional to a variable DC voltage source, pulse generator means connected to said gate signal means for generating a train of pulses in response to said gate signal, selector circuit means coupled to said pulse generator means for selecting an nth pulse and generating an output pulse at the time of said nth pulse, and delay time indicating means having said gate pulse and output pulse coupled thereto for generating an indicating signal initiated at the time of said output pulse and terminated at the initiation of the next succeeding gate pulse.

Claim 10

A delay time indicating circuit comprising means for generating a gate signal having a duration proportional to a variable DC voltage source, pulse generator means connected to said gate signal means for generating a train of pulses in response to said gate signal, selector circuit means coupled to said pulse generator means for selecting an nth pulse and generating an output pulse at the time of said nth pulse, and delay time indicating means having said gate pulse and output pulse coupled thereto for generating an indicating signal initiated at the time of said output pulse and terminated at the initiation of the next succeeding gate pulse.