Multiplexer

Claim 2

A multiplexer for use in a transmission system wherein information signals occurring on a plurality of multiplexer input lines are coupled for transmission over a lesser plurality of common transmission channels coupled to the multiplex output, said multiplexer comprising switch-circuit means having a plurality of inputs for receiving respective ones of said information signals and the like plurality of corresponding outputs with said switch circuit means including logic circuit means coupling the information signal present on any one of said plurality of inputs to the corresponding one of said plurality of outputs when an information signal is present on only said any one of said plurality of inputs and selectively connecting one of more than one information signal simultaneously present on respective ones of said plurality of inputs to the corresponding one of said plurality of outputs when more than one information signal is simultaneously present, said logic circuit means including random pulse generating means coupled thereto to geNerate random control pulses for assigning priority and controlling the selection of connection of one information signal to its corresponding output when more than one information signal is simultaneously present on respective ones of said plurality of inputs.

Claim 3

The multiplexer as set forth in claim 1 wherein priority is assigned under pseudorandom control.

Claim 4

The multiplexer as set forth in claim 1 wherein the said plurality of outputs of said switch circuit means are connected to encoder means for generating an address corresponding to the address of whichever of said outputs provides an information signal at that time.

Claim 5

The multiplexer as set forth in claim 3 wherein said switch circuit means having a plurality of inputs comprises; an input stage including a pair of input logic gate means with one of said pair of input logic gate means responsive to one-half of said plurality of inputs and the other of said pair of input logic gate means responsive to the other half of said plurality of inputs so that each thereby respectively produces a logical output in response to said inputs; and an output stage including a plurality of output logic gate means corresponding in number to said plurality of inputs, each of said output logic gate means having a first input responsive to be controlled by a different one of said plurality of inputs and having a second input responsive to be controlled by the said logical output from one of said pair of input logic gate means.

Claim 6

The multiplexer as set forth in claim 4 wherein said input logic gate means and said output logic gate means are NOR-gate means and wherein the said second input of one-half of said plurality of output logic gate means is responsive to the said logical output of one of said pair of input logic gate means and the said second input of the other half of said plurality of output logic gate means is responsive to the said logical output of the other of said pair of input logic gate means.

Claim 7

A multiplexer system for coupling the information signal and address of individual ones of a plurality of information bearing inputs to transmission channel means comprising; priority switching circuit means having n inputs and n corresponding outputs with logic circuit means coupling said n inputs to said n outputs so that when an information signal is present on only one of said n inputs, said signal is connected to its said corresponding output; random pulse generator means coupled to said logic circuit means to randomly assign priority and control selection of connection of a single information signal when information signals are simultaneously present on more than one of said n inputs; and encoding means having output means and input means with said input means coupled to the said n outputs of said priority switching circuit means so as to generate the address on said output means of that priority switching circuit means input connected through to provide an information signal to the said input means of said encoding means.

Claim 8

A multiplexer system for coupling the information signal and address of individual ones of a plurality of information bearing inputs to transmission channel means comprising; priority switching circuit means having n inputs and n corresponding outputs with logic circuit means coupling said n inputs to said n outputs so that when an information signal is present on only one of said n inputs, said signal is connected to its said corresponding output; random pulse generator means coupled to said logic circuit means to randomly assign priority and control selection of connection of a single information signal when information signals are simultaneously present on more than one of said n inputs; and encoding means having output means and input means with said input means coupled to the said n outputs of said priority switching circuit means so as to generate the address on said output means of that priority switching circuit means input connected through to provide an information signal to the said input means of said encoding means.

Claim 9

The multiplexer system as set forth in claim 6 including circuit means coupled in parallel to both said priority switching circuit means and encoding means for allowing a selected block of information signals to be coupled to said encoding means output prior to generation of the address signal corresponding to the priority switching circuit input providing said block of information signals.

Claim 10

The multiplexing system as set forth in claim 7 wherein said circuit means includes logic circuit means having a first set of n input means coupled respectively to the said n inputs of said priority switching circuit means and having a second set of n input means coupled respectively to the said n outputs of said priority switching circuit means, said logic circuit means further having n output means coupled to the said output means of said encoding means so that said logic circuit means is responsive to coUple said selected block of information signals, under control of said priority switching circuit means, to said encoder output means prior to the said generation of the said address signal corresponding thereto.

Claim 11

A multiplexer system for connecting information signals received from a plurality of stations to transmission channel means comprising: priority switching circuit means having a plurality of inputs coupled respectively to said plurality of stations and a like plurality of associated outputs, said priority switching circuit means acting to connect an information signal received on any one of said inputs to its said associated output when no other input is receiving an information signal; pseudorandom generator means coupled to said priority switching circuit means so that the latter acts to select in a pseudorandom manner one information signal for connection to its said associated output when information signals are simultaneously present on more than one of said plurality of inputs; and encoding means coupled to said priority switching circuit means to generate an address signal on said transmission channel means identifying the station of said plurality of stations that is connected through said priority switching circuit means to said encoder means.

Claim 12

A multiplexer system for connecting information signals received from a plurality of stations to transmission channel means comprising: priority switching circuit means having a plurality of inputs coupled respectively to said plurality of stations and a like plurality of associated outputs, said priority switching circuit means acting to connect an information signal received on any one of said inputs to its said associated output when no other input is receiving an information signal; pseudorandom generator means coupled to said priority switching circuit means so that the latter acts to select in a pseudorandom manner one information signal for connection to its said associated output when information signals are simultaneously present on more than one of said plurality of inputs; and encoding means coupled to said priority switching circuit means to generate an address signal on said transmission channel means identifying the station of said plurality of stations that is connected through said priority switching circuit means to said encoder means.

Claim 13

The multiplexing system as set forth in claim 9 wherein said information signals are divided into words and wherein logic circuit means are coupled between said priority switching circuit means and said transmission channel means so as to connect one of said words to said transmission channel means according to the operation of said priority switching circuit means, said priority switching circuit means acting at the termination of said one of said words to cause said encoding means to generate an address signal corresponding to the address of the station sending said one of said words.

Claim 14

The multiplexer system as set forth in claim 10 wherein said priority switching circuit means comprises: a first decision level stage including first and second logic gate means each having an output and inputs sufficient in number so that said first logic gate means may be coupled to a group of one-half of said plurality of inputs and said second logic gate means may be coupled to a group of the other half of said plurality of inputs; a second decision level stage including four logic gate means each having an output and inputs sufficient in number so that two of said four logic gate means may be coupled respectively to divide said group of one-half of said plurality of inputs again into one-half and the other two of said four logic gate means may be coupled respectively to divide said group of the other half of said plurality of inputs again into one-half; further decision level stages having logic gate means coupled to further divide said groups into halves until said groups are one with each of said first, second and further decision level stages coupled to said pseudorandom generator; and an output stage having a plurality of output logic gate means equal in number to said plurality of inputs to said priority switching circuit means with one input of each of said plurality of output logic gate means respectively coupled to individual ones of the said plurality of inputs, each of said output logic gate means having further inputs equal in number to the number of decision level stages with said further inputs respectively coupled to the said outputs of said logic gate means of said decision level stages so that the simultaneous presence of words on more than one of the said plurality of inputs to said priority switching circuit means results in all but one of said plurality of output logic gate means being blocked.

Claim 15

The multiplexer system as set forth in claim 11 wherein each of said logic gate means comprises NOR-gate means.