Digital timing system

Claim 2

A digital timing system comprising: a. a time base generator for producing output timing pulses; b. a plurality of time pulse counters; c. means connecting each of said time pulse counters to said time base generator; d. digital display means; and e. means switchably connecting said digital display means to each of said time pulse counters to display the time count in each counter without affecting the time count therein and without affecting the continual counting of the counters.

Claim 3

A digital timing system comprising: a. a pulse generator for producing a train of output pulses; b. a pulse rate divider having an input and a plurality of outputs; c. means connecting the input of said pulse rate divider to receive the train of output pulses from said pulse generator; d. a plurality of counter circuits; e. means connecting a different one of said plurality of outputs of said pulse divider to a different one of said plurality of counter circuits each of said counter circuits counting the pulses appearing at the pulse divider output associated therewith; f. means connected to each of said counter circuits whereby each counter circuit can be independently activated to count pulses regardless of the operation of the other counter circuits; g. a digital display means; h. means switchably connecting said digital display means to each of said counter circuits to display the count in each counter without affecting the count therein and without affecting the continual counting of the counters; i. signal producing means for producing a signal indicative of any predetermined count in one of said plurality of counter circuits; j. comparator means for comparing the output of said signal producing means and the output of said one of said counter circuits and for producing a trigger signal when said outputs are equal; and k. means connecting said comparator means to said one counter circuit whereby said counter circuit is reset to zero count when said comparator trigger signal occurs.

Claim 4

A digital timing system comprising: a. a pulse generator for producing a train of output pulses; b. a pulse rate divider having an input and a plurality of outputs; c. means connecting the input of said pulse rate divider to receive the train of output pulses from said pulse generator; d. a plurality of counter circuits; e. means connecting a different one of said plurality of outputs of said pulse divider to a different one of said plurality of counter circuits each of said counter circuits counting the pulses appearing at the pulse divider output associated therewith; f. means connected to each of said counter circuits whereby each counter circuit can be independently activated to count pulses regardless of the operation of the other counter circuits; g. a digital display means; h. means switchably connecting said digital display means to each of said counter circuits to display the count in each counter without affecting the count therein and without affecting the continual counting of the counters; i. signal producing means for producing a signal indicative of any predetermined count in one of said plurality of counter circuits; j. comparator means for comparing the output of said signal producing means and the output of said one of said counter circuits and for producing a trigger signal when said outputs are equal; and k. means connecting said comparator means to said one counter circuit whereby said counter circuit is reset to zero count when said comparator trigger signal occurs.

Claim 5

A digital timing system comprising: a. a pulse generator having a high pulse rate timing pulse output; b. a pulse rate divider circuit connected to the output of said pulse generator, said divider circuit having a first output which provides output pulses at a rate of 1 pulse per second and at least a second output which provides output pulses at a rate of 1 pulse per minute; c. first, second and third counter circuits each having an input and an output; d. means connected to each of said counter circuits whereby each counter circuit can be independently operated to count pulses regardless of the operation of the other counter circuits; e. means connecting the input of said first counter circuit to the second output of said divider circuit, said first counter operating to record a predetermined reference time; f. means connecting the input of said second counter circuit to the second output of said divider circuit, said second counter operating to record total elapsed time of a predetermined event; g. means connecting the input of said third counter circuit to the first output of said divider circuit whereby said third counter, when operating, will count the output pulses therefrom; h. a variable comparator circuit setable over a range of predetermined counts in said third counter circuit; i. means connecting said variable comparator circuit to said third counter circuit, said comparator circuit producing an output signal when the count in said third counter circuit equals a preset count in said comparator; j. means connecting said comparator to said third counter circuit to cause said third counter circuit to begin recounting from zero upon the occurrence of an output signal from said comparator; k. a digital display means; and l. means switchably connecting said digital display means to each of said first, second and third counter circuits to individually display the count in each counter without affecting the count therein or affecting the continued counting of the counters.

Claim 6

A digital timing system comprising: a. a pulse generator having a high pulse rate timing pulse output; b. a pulse rate divider circuit connected to the output of said pulse generator, said divider circuit having a first output which provides output pulses at a rate of 1 pulse per second and at least a second output which provides output pulses at a rate of 1 pulse per minute; c. first, second and third counter circuits each having an input and an output; d. means connected to each of said counter circuits whereby each counter circuit can be independently operated to count pulses regardless of the operation of the other counter circuits; e. means connecting the input of said first counter circuit to the second output of said divider circuit, said first counter operating to record a predetermined reference time; f. means connecting the input of said second counter circuit to the second output of said divider circuit, said second counter operating to record total elapsed time of a predetermined event; g. means connecting the input of said third counter circuit to the first output of said divider circuit whereby said third counter, when operating, will count the output pulses therefrom; h. a variable comparator circuit setable over a range of predetermined counts in said third counter circuit; i. means connecting said variable comparator circuit to said third counter circuit, said comparator circuit producing an output signal when the count in said third counter circuit equals a preset count in said comparator; j. means connecting said comparator to said third counter circuit to cause said third counter circuit to begin recounting from zero upon the occurrence of an output signal from said comparator; k. a digital display means; and l. means switchably connecting said digital display means to each of said first, second and third counter circuits to individually display the count in each counter without affecting the count therein or affecting the continued counting of the counters.

Claim 7

A digital timing system comprising: a. a counter circuit having an input adapted to receive timing pulses and to count the same; b. a variable comparator circuit; c. means for selectively setting said variable comparator circuit over a range of predetermined counts in said counter circuit; d. means connecting said variable comparator circuit to said counter circuit, said comparator circuit producing an output signal when the count in said counter circuit equals a preset count in said comparator; and e. means connecting said comparator to said counter circuit to cause said counter circuit to reset and to begin recounting upon the occurrence of an output signal from said comparator.

Claim 8

A digital timing system comprising: a. a counter circuit having an input adapted to receive timing pulses and to count the same; b. a variable comparator circuit; c. means for selectively setting said variable comparator circuit over a range of predetermined counts in said counter circuit; d. means connecting said variable comparator circuit to said counter circuit, said comparator circuit producing an output signal when the count in said counter circuit equals a preset count in said comparator; and e. means connecting said comparator to said counter circuit to cause said counter circuit to reset and to begin recounting upon the occurrence of an output signal from said comparator.

Claim 9

A digital timing system as defined in claim 4 wherein said counter has an output connected to a digital display.

Claim 10

A digital timing system as defined in claim 3 wherein said digital display means is a neon display and wherein said means switchably connecting said digital display means to each of said first, second and third counter circuits includes a binary to decimal decoder circuit.

Claim 11

A digital timing system as defined in claim 1 for use in aviation flight timing and wherein one of said plurality of counters records Greenwich Mean Time, a second of said plurality of counters records total elapsed flight time and a third of said plurality of counters records aircraft landing approach time.

Claim 12

A digital timing system comprising: a. a counter circuit having an input adapted to receive timing pulses and to count the same; b. a variable comparator circuit selectively settable over a range of predetermined counts in said counter circuit; and c. means connecting said variable comparator circuit to said counter circuit, said comparator circuit operable to cause said counter circuit to begin recounting from zero after the occurrence of a predetermined number of timing pulses, the predetermined number of timing pulses being determined by the setting of said variable comparator.

Claim 13

A digital timing system comprising: a. a counter circuit having an input adapted to receive timing pulses and to count the same; b. a variable comparator circuit selectively settable over a range of predetermined counts in said counter circuit; and c. means connecting said variable comparator circuit to said counter circuit, said comparator circuit operable to cause said counter circuit to begin recounting from zero after the occurrence of a predetermined number of timing pulses, the predetermined number of timing pulses being determined by the setting of said variable comparator.

Claim 14

A digital timing system comprising: a. a counter circuit having an input adapted to receive timing pulses and to count the same; b. a digital display means connected to said counter circuit to display the pulse count therein, each digit of said digital display having a decimal point associated therewith, each of said decimal points being operable between a deenergized and an energized state; c. means connected to one of said decimal points to energize the same to separate the digital display in a predetermined manner; d. a variable comparator circuit setable over a range of predetermined counts in said counter circuit; e. means connecting said variable comparator circuit to said counter circuit, said comparator circuit producing an output signal when the count in said counter circuit equals a preset count in said comparator; f. means connecting said comparator to said counter circuit to cause said counter circuit to reset and to begin recounting upon the occurrence of an output signal from said comparator; and g. means connected to said digital display means to energize all of said decimal points when said counter circuit is reset.

Claim 15

A digital timing system comprising: a. a counter circuit having an input adapted to receive timing pulses and to count the same; b. a digital display means connected to said counter circuit to display the pulse count therein, each digit of said digital display having a decimal point associated therewith, each of said decimal points being operable between a deenergized and an energized state; c. means connected to one of said decimal points to energize the same to separate the digital display in a predetermined manner; d. a variable comparator circuit setable over a range of predetermined counts in said counter circuit; e. means connecting said variable comparator circuit to said counter circuit, said comparator circuit producing an output signal when the count in said counter circuit equals a preset count in said comparator; f. means connecting said comparator to said counter circuit to cause said counter circuit to reset and to begin recounting upon the occurrence of an output signal from said comparator; and g. means connected to said digital display means to energize all of said decimal points when said counter circuit is reset.

Claim 16

A digital timing system as set forth in claim 9 which further includes means for manually clearing said counter circuit and means connected to said counter circuit to prevent automatic resetting of said counter circuit more than once until said counter has been manually cleared.

Claim 17

A digital timiNg system comprising: a. a pulse counter circuit having a timing input, in reset input and an output; b. first AND gate means having first and second input and an output; c. a timing pulse generator for producing timing pulses at its output; d. means connecting the output of said timing pulse generator to the first input of said first AND gate; e. means connecting the output of said first AND gate to the timing input of said pulse counter circuit; f. second AND gate means having first and second inputs and an output; g. first switch means having a first stationary contact, a second stationary contact and a movable contact; h. means connecting the second input of said first AND gate to the first stationary contact of said first switch means; i. means connecting the first input of said second AND gate to the second stationary contact of said first switch means; j. means connecting the second input of said second AND gate through a momentary switch to a signal source suitable for enabling said second AND gate; k. means connecting the movable contact of said first switch means to a signal source suitable for enabling said first and second AND gates: l. means connecting the output of said second AND gate to the reset input of said pulse counter circuit; and m. a digital display means connected to the output of said pulse counter circuit to display the pulse count therein.

Claim 18

A digital timiNg system comprising: a. a pulse counter circuit having a timing input, in reset input and an output; b. first AND gate means having first and second input and an output; c. a timing pulse generator for producing timing pulses at its output; d. means connecting the output of said timing pulse generator to the first input of said first AND gate; e. means connecting the output of said first AND gate to the timing input of said pulse counter circuit; f. second AND gate means having first and second inputs and an output; g. first switch means having a first stationary contact, a second stationary contact and a movable contact; h. means connecting the second input of said first AND gate to the first stationary contact of said first switch means; i. means connecting the first input of said second AND gate to the second stationary contact of said first switch means; j. means connecting the second input of said second AND gate through a momentary switch to a signal source suitable for enabling said second AND gate; k. means connecting the movable contact of said first switch means to a signal source suitable for enabling said first and second AND gates: l. means connecting the output of said second AND gate to the reset input of said pulse counter circuit; and m. a digital display means connected to the output of said pulse counter circuit to display the pulse count therein.

Claim 19

A digital timing system as set forth in claim 11 wherein a variable comparator circuit, setable over a range of predetermined counts in said counter circuit, is connected to the output of said pulse counter circuit, said comparator circuit producing an output signal when the count in said pulse counter circuit equals a preset count in said comparator and wherein the output of said comparator is connected to the reset input of said pulse counter circuit to cause said counter circuit to reset and to begin recounting upon the occurrence of an output signal from said comparator.