Generator with differential digital-to-analog converter

Claim 2

A vector generator in which X- and Y- axis deflection signals are produced in order to generate vectors at any desired writing rate, said generator comprising: X- and Y-axis circuits each including, a plurality of input lines over which a plurality of incoming signals containing logical functions are applied, a pair of parallel-connected gates associated with each of said input lines to which the incoming signals are applied, and a separate register associated with each of said gates to which the output from each of said gates is applied; means for controlling the alternate opening and closing of said gates; means for generating time function ramp signals; a separate digital-to-analog conversion means to which the output from each pair of registers corresponding to each incoming signal is applied and to which the ramp signals are applied, said separate digital-to-analog conversion means including a single ladder network for deriving analog signals; and means corresponding to each of said axes for summing thE output of said X-axis single ladder network and the output of said Y-axis single ladder network to produce a deflection signal.

Claim 3

A generator as set forth in claim 1 wherein: said means for controlling the alternate opening and closing of said gates is a divide by two flip-flop whose output is fed to each of said gates and also to said means for generating said ramp signals in order to control the direction of slope of the ramp signals generated.

Claim 4

A generator as set forth in claim 1 wherein: each of said conversion means includes a digital-to-analog switch comprising a switching transistor for each logical function and switching logic coupled to each switch to permit operation thereof.

Claim 5

A generator as set forth in claim 3 wherein: said switching transistors are field effect transistors and the switching logic coupled to each switching transistor includes a NAND-gate for gating the incoming digital signal and a driving transistor coupled between said NAND-gate and the associated switching transistor for providing required driving power.

Claim 6

A vector generator in which X- and Y-axis deflection signals are produced in order to generate vectors at any desired writing rate, said generator comprising: X- and Y-axis circuits each including, a plurality of input lines over which a plurality of input digital signals representing each bit of a desired vector are applied, a pair of parallel connected gates connected to each of said input lines for alternately gating each of said input digital signals, and a separate register connected to each of said gates for storing the gated output from each of said gates; a ramp generator for generating time function ramp signals; a divide by two flip-flop whose output is fed to each of said gates for controlling the alternate opening and closing of said gates and also fed to said ramp generator for controlling the direction of slope of the ramp signals generated; a separate digital-to-analog conversion means coupled to the outputs of each pair of registers corresponding to each input digital signal and also coupled to the ramp signals from said ramp generator, said conversion means converting the digital signals to analog signals, said separate digital-to-analog conversion means including a single ladder network for deriving output analog signals; and means corresponding to each of said axes for summing the output of said X-axis single ladder network and said Y-axis single ladder network to produce a deflection signal.

Claim 7

A vector generator in which X- and Y-axis deflection signals are produced in order to generate vectors at any desired writing rate, said generator comprising: X- and Y-axis circuits each including, a plurality of input lines over which a plurality of input digital signals representing each bit of a desired vector are applied, a pair of parallel connected gates connected to each of said input lines for alternately gating each of said input digital signals, and a separate register connected to each of said gates for storing the gated output from each of said gates; a ramp generator for generating time function ramp signals; a divide by two flip-flop whose output is fed to each of said gates for controlling the alternate opening and closing of said gates and also fed to said ramp generator for controlling the direction of slope of the ramp signals generated; a separate digital-to-analog conversion means coupled to the outputs of each pair of registers corresponding to each input digital signal and also coupled to the ramp signals from said ramp generator, said conversion means converting the digital signals to analog signals, said separate digital-to-analog conversion means including a single ladder network for deriving output analog signals; and means corresponding to each of said axes for summing the output of said X-axis single ladder network and said Y-axis single ladder network to produce a deflection signal.

Claim 8

A vector generator in which X- and Y-axis deflection signals are produced in order to generate vectors at any desired writing rate, said generator comprising: X- and Y-axis circuits each including, a plurality of input lines over which a plurality of input digital signals representing each bit of a desired vector are applied, a pair of parallel connected gates connected to each of said input lines for alternately gating each of said input digital signals, and a separate register connected to each of said gates for storing the gated output from each of said gates; a ramp generator for generating time function ramp signals; a divide by two flip-flop whose output is fed to each of said gates for controlling the alternate opening and closing of said gates and also fed to said ramp generator for controlling the direction of slope of the ramp signals generated; a separate digital-to-analog conversion means coupled to the outputs of each pair of registers corresponding to each input digital signal and also coupled to the ramp signals from said ramp generator, said conversion means converting the digital signals to analog signals, each of said conversion means including a digital-to-analog switch comprising a switching transistor for each logical function input thereto and switching logic coupled to each switch to permit operation therEof, said separate digital-to-analog conversion means further including a single ladder network for deriving analog output signals; and means corresponding to each of said axes for summing the output of said X-axis single ladder network and the output of said Y-axis single ladder network to produce a deflection signal.

Claim 9

A vector generator in which X- and Y-axis deflection signals are produced in order to generate vectors at any desired writing rate, said generator comprising: X- and Y-axis circuits each including, a plurality of input lines over which a plurality of input digital signals representing each bit of a desired vector are applied, a pair of parallel connected gates connected to each of said input lines for alternately gating each of said input digital signals, and a separate register connected to each of said gates for storing the gated output from each of said gates; a ramp generator for generating time function ramp signals; a divide by two flip-flop whose output is fed to each of said gates for controlling the alternate opening and closing of said gates and also fed to said ramp generator for controlling the direction of slope of the ramp signals generated; a separate digital-to-analog conversion means coupled to the outputs of each pair of registers corresponding to each input digital signal and also coupled to the ramp signals from said ramp generator, said conversion means converting the digital signals to analog signals, each of said conversion means including a digital-to-analog switch comprising a switching transistor for each logical function input thereto and switching logic coupled to each switch to permit operation therEof, said separate digital-to-analog conversion means further including a single ladder network for deriving analog output signals; and means corresponding to each of said axes for summing the output of said X-axis single ladder network and the output of said Y-axis single ladder network to produce a deflection signal.

Claim 10

A generator as set forth in claim 6 wherein: said switching transistors are field effect transistors and the switching logic coupled to each switching transistor includes a NAND-gate for gating the incoming digital signal and a driving transistor coupled between said NAND-gate and the associated switching transistor for providing required driving power.