Variable frequency control

Claim 2

In a system for controlling the output frequency of a variable frequency source as set forth in claim 1 wherein said means responsive to the last remainder frequency includes means for determining if the last remainder is equal to the error frequency or the output frequency of said divider means less the error frequency.

Claim 3

In a system for controlling the output frequency of a variable frequency source as set forth in claim 1 wherein said means responsive to the last remainder frequency includes means for completing one subtraction of the output frequency of said divider means from the desired frequency signal when the remainder frequency equals the output frequency of said divider means less the error frequency.

Claim 4

In a system for controlling the output frequency of a variable frequency source, comprising: control means responsive to a desired frequency input and an error frequency input for generating a control signal to the variable source to establish an output frequency therefrom, divider means responsive to the output frequency of the variable source for producing an output frequency locked at the submultiple of the actual frequency, lock control means responsive to the output of said divider means for generating a frequency-lock signal to said divider means to fix the output thereof at a predetermined fraction of the source frequency output, and means for subtracting the output frequency of said divider means from the desired frequency signal in a manner that produces an output therefrom equal to the error frequency signal representing the difference between the desired frequency of the variable source and the actual frequency of said source, said error frequency signal connected to the error frequency input of said control means.

Claim 5

In a system for controlling the output frequency of a variable frequency source as set forth in claim 5 wherein said means for subtracting the output frequency of said divider means from the desired frequency signal produces the error frequency signal in accordance with the equAtion: fd-Nfso - or + Delta f, where fd equals the desired frequency, Nfso equals the actual frequency of the variable source, and Delta f equals the error frequency signal.

Claim 6

In a system for controlling the output frequency of a variable frequency source as set forth in claim 5 wherein said means for subtracting the output frequency of said divider means from the desired frequency signal includes logic circuitry for repetitively subtracting the two frequency signals to produce the error frequency signal.

Claim 7

In a system for controlling the output frequency of a variable frequency source as set forth in claim 5 wherein said divider means includes a tunnel diode oscillator having an input connected to the variable source and an output frequency at a submultiple of the input thereto and including a variable biasing network for said tunnel diode oscillator to set the output at a submultiple of the input.

Claim 8

In a system for controlling the output frequency of a variable frequency source as set forth in claim 5 wherein said lock control means includes a threshold detector generating an adjusting signal when the output of said divider means varies from a submultiple of the variable frequency source output.

Claim 9

In a system for controlling the output frequency of a variable frequency source as set forth in claim 10 including a bias network control means responsive to the adjusting signal for generating the frequency-lock signal connected to the variable biasing network for said tunnel diode oscillator.

Claim 10

In a system for controlling the output frequency of a variable frequency source, comprising: control means responsive to a desired frequency input and an error frequency input for generating a control signal to the variable source, divider means responsive to the output of the frequency source for producing a frequency locked at a submultiple of the source frequency, means for converting the frequency output of said divider means into a digital bit stream representative thereof, register means for receiving and storing the digital bit stream from said converting means, second register means for receiving and storing a digital bit stream representative of the desired frequency of said variable source, means for subtracting the output of said first register means from said second register means repetitively until the output therefrom equals the error frequency signal between the desired frequency of the variable source and the actual frequency of said source, and means for coupling the error frequency signal to the error frequency input of said control means.

Claim 11

In a system for controlling the output frequency of a variable frequency source as set forth in claim 11 wherein said means for converting the frequency output of said divider means includes a pulse frequency counter and a timing gate for passing the frequency output of said divider means to said counter for a fixed time interval.

Claim 12

In a system for controlling the output frequency of a variable frequency source as set forth in claim 12 wherein said means for subtracting the digital bit streams of said registers includes: means for generating the two''s complement of the digital bit stream in said first register, and means for adding the two''s complement code to the desired frequency code transferred from said second register to produce an error frequency input to said control means.

Claim 13

In a system for controlling the output frequency of a variable frequency source as set forth in claim 13 including timing means for establishing the sequence of operation of said first and second registers and said means for adding the two''s complement code to the digital bit stream representing a desired frequency.

Claim 14

In a system for controlling the output frequency of a variable frequency source as set forth in claim 11 wherein said control means includes: a third register for receiving and storing a bit stream representing the combination of a desired frequency and an error frequency, and a digital-to-analog converter for converting the code of said third register into an analog signal for controlling said frequency source.

Claim 15

In a system for controlling the output frequency of a variable frequency source, comprising: control means responsive to a desired frequency input and an error frequency input for generating a control signal to the variable source, divider means responsive to the output of the frequency source for producing a frequency locked at a submultiple of the source frequency, lock control means responsive to the output of said divider means for generating a frequency-lock signal to said divider means to fix the output thereof at a predetermined submultiple of the source frequency output, means for converting the frequency output of said divider means into a digital bit stream representative thereof, register means for receiving and storing the digital bit stream from said converting means, second register means for receiving and storing a digital bit stream representative of the desired frequency of said variable source, means for subtracting the output of said first register means from said second register means repetitively until the output therefrom equals the error frequency signal between the desired frequency of the variable source and the actual frequency of said source, and means for coupling the error frequency signal to the input of said control means.

Claim 16

In a system for controlling the output frequency of a variable frequency source as set forth in claim 16 wherein said divider means includes a tunnel diode oscillator having an input connected to the variable source and an output frequency at a submultiple of the input thereto and including a variable biasing network for said tunnel diode oscillator to set the output at a submultiple of the input.

Claim 17

In a system for controlling the output frequency of a variable frequency source as set forth in claim 17 wherein said lock control means includes a threshold detector generating an adjusting signal when the output of said divider means varies from a locked-in submultiple of the variable frequency source output.

Claim 18

In a system for controlling the output frequency of a variable frequency source as set forth in claim 18 including a bias network control means responsive to the adjusting signal for generating the frequency-lock signal connected to the variable biasing network for said tunnel diode oscillator.

Claim 19

In a system for controlling the output frequency of a variable frequency source as set forth in claim 19 wherein said means for subtracting the digital bit streams of said registers includes: means for generating the two''s complement of the digital bit stream in said first register, and means for adding the two''s complement code to the desired frequency code transferred from said second register to produce an error frequency input to said control means.

Claim 20

In a system for controlling the output frequency of a variable frequency source as set forth in claim 20 wherein said control means includes: a third register for receiving and storing a bit stream representing the desired frequency and a bit stream representing the error frequency, and a digital-to-analog converter for converting the code of said third register into an analog signal for controlling said frequency source.