Circular interpolation system

Claim 2

A digital computer system, a. a pulse code unit 76 having an input 536 for receiving a series of 10 input pulses (FIG. 5) in each cycle of operation, said pulse code unit 76 having four noncarry outputs 145-148 and a carry output 151 and being operable in each cycle of operation to produce respective series of noncarry pulses (FIG. 5) at the respective four noncarry outputs and produce a carry pulse (FIG. 5) at said carry output, with the numbers of noncarry pulses in said series being selectively addable to produce any number from one through nine and with the noncarry pulses of each series being noncoincident with the carry pulse and with the noncarry pulses of each of the other series, b. a series of accumulator register decade units 71-75 for storing respective decimal digits therein and connected in cascade for representing successive decimal orders, and including a lowest order accumulator register decade unit, a highest order accumulator register decade unit and intervening order accumulator register decade units representing decimal orders intervening between the lowest order and the highest order of said successive decimal orders, each accumulator register decade unit comprising a decade counter 111-114 having a decade counter input circuit 119 and a decade counter output circuit 161, c. respective sets of four gates 122-125 having outputs connected to the respective decade counter input circuits 119 of the respective accumulator register decade units 71-75, each set of four gates 122-125 having at least two inputs per gate, one such input being connected to a respective one of the noncarry outputs 145-148 and other such input being controlled by a respective bit of a plural order coded decimal signal having respective weights at its successive bit positions corresponding to the numbers of noncarry pulses of the respective series and having respective orders corresponding to the successive decimal orders represented by said series of accumulator register decade units, said sets of gates 122-125 thereby being controllable to supply numbers of noncarry pulses to the decade counter input circuits 119 of the respective accumulator register decade units simultaneously in accOrdance with said plural order coded decimal signal, in each cycle of operation of said pulse code unit, d. said accumulator register decade units 71-75 each including a carry storage circuit 173 connected with the decade counter output circuit 161 thereof for assuming an active condition in response to a decade carry pulse from such decade counter output circuit 161 at a count of 10 of the decade counter 111114 thereof, without transmission of said decade carry pulse to the input circuit 119 of the next succeeding accumulator register decade unit, e. said carry storage circuits 173 of the respective accumulator register decade units being all connected with the carry output 151 of said pulse code unit 76 for receipt of the carry pulse therefrom, said carry storage circuits 173 when in said active condition being responsive to a carry pulse from said pulse code unit 76 to transmit an effective carry pulse to the decade counter input circuit 119 of the next succeeding accumulator register decade unit to provide for the counting of such effective carry pulses, and whereby said plural order coded decimal signal may be altered during the time of the carry pulses from the carry output 151 of said pulse code unit 76.

Claim 3

In a digital computer system, a. an operational integator 41 comprising an integrand register 81-85 and an accumulator register 71-75 including, respectively, serially connected integrand decade units 261-264, and serially connected accumulator decade units 111-114, with bistable carry storage circuits 173 interposed between the output 161 of each accumulator decade unit and the input 119 of the next succeeding accumulator decade unit, b. a parallel transfer circuit 317-320 operative with a 1, 1'', 2, 5 code for applying information in parallel to respective stages 261, 262, 263, and 264 of each decade unit of said integrand register 81-85, with the successive stages 261-264 thus representing weights of 1, 1, 2 and 5, respectively, c. respective sets of gates 122-125 connected with the inputs 119 of the respective accumulator decade units, each set of gates 122-125 being operatively controlled in parallel by respective stages 264, 263, 262, and 261 of a corresponding integrand decade unit in such 1, 1'', 2, 5 code, and d. a 5, 2, 1'', 1 pulse code unit 76 having noncarry outputs 145-148 connected to the respective gates 122-125 of each of said sets of gates 122-125, and having a carry output 151, said pulse code unit 76 being responsive, during a cycle of operation thereof, to a series of 10 input pulses (FIG. 5) to generate at a first noncarry output 145 five noncarry pulses, at a second noncarry output 146 two noncarry pulses, at a third noncarry output 147 one noncarry pulse, and at a fourth noncarry output 148 one noncarry pulse, respectively, and to generate a carry pulse at said carry output 151 which is subsequent to said noncarry pulses, with transmission by each set of gates 122-125 to the input 119 of the associated accumulator decade unit of a number of noncarry pulses corresponding to the digit registered by the associated integrand decade unit in said 1, 1'', 2, 5 code, said pulse code unit 76 being responsive to said series of 10 input pulses to simultaneously operate all of said accumulator decade units 71-75 through an addition cycle to cause each accumulator decade unit to add to a number stored therein at the beginning of each cycle of operation of said pulse code unit 76, a number corresponding to the number of noncarry pulses supplied thereto by the associated set of gates 122-125 during said cycle of operation, and corresponding to the number registered by the associated integrand decade unit, any decade carry pulses caused by a count of 10 of the respective accumulator decade units 72-75 serving to set the respective associated bistable carry storage circuit 173 without transmission of suCh decade carry pulses to the input 119 of the following accumulator decade unit, e. said bistable carry storage circuits 173 being connected to the carry output 151 of said pulse code unit 76 to receive said carry pulse therefrom and being responsive to such carry pulse, when in set condition, to transmit an effective carry pulse to the input 119 of the next succeeding accumulator decade unit for counting thereby, whereby the number registered by said integrand register 81-85 may be changed during the output of the carry pulse from the carry output 151 of the pulse code unit 76 without spuriously affecting the number of noncarry pulses transmitted by said sets of gates 122-125.

Claim 4

In a digital computer system, a. an operational integator 41 comprising an integrand register 81-85 and an accumulator register 71-75 including, respectively, serially connected integrand decade units 261-264, and serially connected accumulator decade units 111-114, with bistable carry storage circuits 173 interposed between the output 161 of each accumulator decade unit and the input 119 of the next succeeding accumulator decade unit, b. a parallel transfer circuit 317-320 operative with a 1, 1'', 2, 5 code for applying information in parallel to respective stages 261, 262, 263, and 264 of each decade unit of said integrand register 81-85, with the successive stages 261-264 thus representing weights of 1, 1, 2 and 5, respectively, c. respective sets of gates 122-125 connected with the inputs 119 of the respective accumulator decade units, each set of gates 122-125 being operatively controlled in parallel by respective stages 264, 263, 262, and 261 of a corresponding integrand decade unit in such 1, 1'', 2, 5 code, and d. a 5, 2, 1'', 1 pulse code unit 76 having noncarry outputs 145-148 connected to the respective gates 122-125 of each of said sets of gates 122-125, and having a carry output 151, said pulse code unit 76 being responsive, during a cycle of operation thereof, to a series of 10 input pulses (FIG. 5) to generate at a first noncarry output 145 five noncarry pulses, at a second noncarry output 146 two noncarry pulses, at a third noncarry output 147 one noncarry pulse, and at a fourth noncarry output 148 one noncarry pulse, respectively, and to generate a carry pulse at said carry output 151 which is subsequent to said noncarry pulses, with transmission by each set of gates 122-125 to the input 119 of the associated accumulator decade unit of a number of noncarry pulses corresponding to the digit registered by the associated integrand decade unit in said 1, 1'', 2, 5 code, said pulse code unit 76 being responsive to said series of 10 input pulses to simultaneously operate all of said accumulator decade units 71-75 through an addition cycle to cause each accumulator decade unit to add to a number stored therein at the beginning of each cycle of operation of said pulse code unit 76, a number corresponding to the number of noncarry pulses supplied thereto by the associated set of gates 122-125 during said cycle of operation, and corresponding to the number registered by the associated integrand decade unit, any decade carry pulses caused by a count of 10 of the respective accumulator decade units 72-75 serving to set the respective associated bistable carry storage circuit 173 without transmission of suCh decade carry pulses to the input 119 of the following accumulator decade unit, e. said bistable carry storage circuits 173 being connected to the carry output 151 of said pulse code unit 76 to receive said carry pulse therefrom and being responsive to such carry pulse, when in set condition, to transmit an effective carry pulse to the input 119 of the next succeeding accumulator decade unit for counting thereby, whereby the number registered by said integrand register 81-85 may be changed during the output of the carry pulse from the carry output 151 of the pulse code unit 76 without spuriously affecting the number of noncarry pulses transmitted by said sets of gates 122-125.

Claim 5

In a digital computer system, a. an operational integator 41 comprising an integrand register 81-85 and an accumulator register 71-75 including, respectively, serially connected integrand decade units 81-85, and serially connected accumulator decade units 71-75, with bistable carry storage circuits 173 interposed between the output 161 of each accumulator decade unit and the input 119 of the next succeeding accumulator decade unit, b. respective sets of gates 122-125 connected with the inputs 119 of the respective accumulator decade units, each set of gates 122-125 being operatively controlled in parallel by respective stages 264, 263, 262, and 261 of a corresponding integrand decade unit, and c. a pulse code unit 76 having noncarry outputs 145-148 connected to the respective gates 122-125 of each of said sets of gates 122-125 and having a carry output 151, said pulse code unit 76 being responsive, during a cycle of operation thereof, to a series of 10 input pulses to produce four series of noncarry pulses at the respective noncarry outputs 145-148 and a carry pulse at the carry output 151, with the numbers of noncarry pulses in said series being selectively addable by control of said gates 122-125 to produce at the inputs 119 of the respective accumulator decade units any number of noncarry pulses from 1 through 9, and with the noncarry pulses of each series being noncoincident with the carry pulse and noncoincident with the noncarry pulses of each of the other series, with transmission by each set of gates 122-125 to the input 119 of the associated accumulator decade unit of a number of noncarry pulses corresponding to the digit registered by the associated integrand decade unit, said pulse code unit 76 being responsive to said series of 10 input pulses to simultaneously operate all of said accumulator decade units 71-75 through an addition cycle to cause each accumulator decade unit to add to a number stored therein at the beginning of each cycle of operation of said pulse code unit 76, a number corresponding to the number of noncarry pulses supplied thereto by the associated set of gates 122-125 during said cycle of operation, any decade carry pulses caused by a count of 10 of the respective accumulator decade units 71-75 serving to set the respective associated bistable carry storage circuit 173 without transmission of such decade carry pulses to the input 119 of the following accumulator decade unit, d. said bistable carry storage circuits 173 being connected to the carry output 151 of said pulse code unit 76 to receive said carry pulse therefrom and being responsive to such carry pulse, when in set condition, to transmit an effective carry pulse to the input 119 of the next succeeding accumulator decade unit for counting thereby, whereby the number registered by said integrand register 81-85 may be changed during the output of the carry pulse from the carry output 151 of the pulse code unit 76 without interfering with the transmission of noncarry pulses by said sets of gates 122-125.

Claim 6

In a digital computer system, a. an operational integator 41 comprising an integrand register 81-85 and an accumulator register 71-75 including, respectively, serially connected integrand decade units 81-85, and serially connected accumulator decade units 71-75, with bistable carry storage circuits 173 interposed between the output 161 of each accumulator decade unit and the input 119 of the next succeeding accumulator decade unit, b. respective sets of gates 122-125 connected with the inputs 119 of the respective accumulator decade units, each set of gates 122-125 being operatively controlled in parallel by respective stages 264, 263, 262, and 261 of a corresponding integrand decade unit, and c. a pulse code unit 76 having noncarry outputs 145-148 connected to the respective gates 122-125 of each of said sets of gates 122-125 and having a carry output 151, said pulse code unit 76 being responsive, during a cycle of operation thereof, to a series of 10 input pulses to produce four series of noncarry pulses at the respective noncarry outputs 145-148 and a carry pulse at the carry output 151, with the numbers of noncarry pulses in said series being selectively addable by control of said gates 122-125 to produce at the inputs 119 of the respective accumulator decade units any number of noncarry pulses from 1 through 9, and with the noncarry pulses of each series being noncoincident with the carry pulse and noncoincident with the noncarry pulses of each of the other series, with transmission by each set of gates 122-125 to the input 119 of the associated accumulator decade unit of a number of noncarry pulses corresponding to the digit registered by the associated integrand decade unit, said pulse code unit 76 being responsive to said series of 10 input pulses to simultaneously operate all of said accumulator decade units 71-75 through an addition cycle to cause each accumulator decade unit to add to a number stored therein at the beginning of each cycle of operation of said pulse code unit 76, a number corresponding to the number of noncarry pulses supplied thereto by the associated set of gates 122-125 during said cycle of operation, any decade carry pulses caused by a count of 10 of the respective accumulator decade units 71-75 serving to set the respective associated bistable carry storage circuit 173 without transmission of such decade carry pulses to the input 119 of the following accumulator decade unit, d. said bistable carry storage circuits 173 being connected to the carry output 151 of said pulse code unit 76 to receive said carry pulse therefrom and being responsive to such carry pulse, when in set condition, to transmit an effective carry pulse to the input 119 of the next succeeding accumulator decade unit for counting thereby, whereby the number registered by said integrand register 81-85 may be changed during the output of the carry pulse from the carry output 151 of the pulse code unit 76 without interfering with the transmission of noncarry pulses by said sets of gates 122-125.

Claim 7

In a digital computer system, a. an operational integator 41 comprising an integrand register 81-85 and an accumulator register 71-75 including, respectively, serially connected inTegrand decade units 81-85, and serially connected accumulator decade units 71-75, with bistable carry storage circuits 173 interposed between the output 161 of each accumulator decade unit and the input 119 of the next succeeding accumulator decade unit, b. respective sets of gates 122-125 connected with the inputs 119 of the respective accumulator decade units, each set of gates 122-125 being operatively controlled in parallel by respective stages 264, 263, 262, and 261 of a corresponding integrand decade unit, c. a pulse code unit 76 having noncarry outputs 145-148 connected to the respective gates 122-125 of each of said sets of gates 122-125 and having a carry output 151, said pulse code unit 76 being responsive, during a cycle of operation thereof, to a series of 10 input pulses to produce four series of noncarry pulses at the respective noncarry outputs 145-148 and a carry pulse at the carry output 151, with the numbers of noncarry pulses in said series being selectively addable by control of said gates 122-125 to produce at the inputs 119 of the respective accumulator decade units any number of noncarry pulses from 1 through 9, and with the noncarry pulses of each series being noncoincident with the carry pulse and noncoincident with the noncarry pulses of each of the other series, with transmission by each set of gates 122-125 to the input 119 of the associated accumulator decade unit of a number of noncarry pulses corresponding to the digit registered by the associated integrand decade unit, said pulse code unit 76 being responsive to said series of 10 input pulses to simultaneously operate all of said accumulator decade units 71-75 through an addition cycle to cause each accumulator decade unit to add to a number stored therein at the beginning of each cycle of operation of said pulse code unit 76, a number corresponding to the number of noncarry pulses supplied thereto by the associated set of gates 122-125 during said cycle of operation, any decade carry pulses caused by a count of 10 of the respective accumulator decade units 71-75 serving to set the respective associated bistable carry storage circuit 173 without transmission of such decade carry pulses to the input 119 of the following accumulator decade unit, d. said bistable carry storage circuits 173 being connected to the carry output 151 of said pulse code unit 76 to receive said carry pulse therefrom and being responsive to such carry pulse, when in set condition, to transmit an effective carry pulse to the input 119 of the next succeeding accumulator decade unit for counting thereby, whereby the number registered by said integrand register 81-85 may be changed during the output of the carry pulse from the carry output 151 of the pulse code unit 76 without interfering with the transmission of noncarry pulses by said sets of gates 122-125, and e. a serial connection circuit 266-275 for connecting said integrand decade units 261-264 in series for serially counting pulses supplied to an input 281 of said integrand register 81-85, and said integrand register 81-85 being responsive to pulses supplied to its input 281 during the time of generation of said carry pulse at said carry output 151 of said pulse code unit 76 to provide for serial modification of the number stored in aid integrand register without interfering with the transmission of noncarry pulses by said sets of gates 122-125.

Claim 8

In a digital computer system, a. an operational integator 41 comprising an integrand register 81-85 and an accumulator register 71-75 including, respectively, serially connected inTegrand decade units 81-85, and serially connected accumulator decade units 71-75, with bistable carry storage circuits 173 interposed between the output 161 of each accumulator decade unit and the input 119 of the next succeeding accumulator decade unit, b. respective sets of gates 122-125 connected with the inputs 119 of the respective accumulator decade units, each set of gates 122-125 being operatively controlled in parallel by respective stages 264, 263, 262, and 261 of a corresponding integrand decade unit, c. a pulse code unit 76 having noncarry outputs 145-148 connected to the respective gates 122-125 of each of said sets of gates 122-125 and having a carry output 151, said pulse code unit 76 being responsive, during a cycle of operation thereof, to a series of 10 input pulses to produce four series of noncarry pulses at the respective noncarry outputs 145-148 and a carry pulse at the carry output 151, with the numbers of noncarry pulses in said series being selectively addable by control of said gates 122-125 to produce at the inputs 119 of the respective accumulator decade units any number of noncarry pulses from 1 through 9, and with the noncarry pulses of each series being noncoincident with the carry pulse and noncoincident with the noncarry pulses of each of the other series, with transmission by each set of gates 122-125 to the input 119 of the associated accumulator decade unit of a number of noncarry pulses corresponding to the digit registered by the associated integrand decade unit, said pulse code unit 76 being responsive to said series of 10 input pulses to simultaneously operate all of said accumulator decade units 71-75 through an addition cycle to cause each accumulator decade unit to add to a number stored therein at the beginning of each cycle of operation of said pulse code unit 76, a number corresponding to the number of noncarry pulses supplied thereto by the associated set of gates 122-125 during said cycle of operation, any decade carry pulses caused by a count of 10 of the respective accumulator decade units 71-75 serving to set the respective associated bistable carry storage circuit 173 without transmission of such decade carry pulses to the input 119 of the following accumulator decade unit, d. said bistable carry storage circuits 173 being connected to the carry output 151 of said pulse code unit 76 to receive said carry pulse therefrom and being responsive to such carry pulse, when in set condition, to transmit an effective carry pulse to the input 119 of the next succeeding accumulator decade unit for counting thereby, whereby the number registered by said integrand register 81-85 may be changed during the output of the carry pulse from the carry output 151 of the pulse code unit 76 without interfering with the transmission of noncarry pulses by said sets of gates 122-125, and e. a serial connection circuit 266-275 for connecting said integrand decade units 261-264 in series for serially counting pulses supplied to an input 281 of said integrand register 81-85, and said integrand register 81-85 being responsive to pulses supplied to its input 281 during the time of generation of said carry pulse at said carry output 151 of said pulse code unit 76 to provide for serial modification of the number stored in aid integrand register without interfering with the transmission of noncarry pulses by said sets of gates 122-125.

Claim 9

In a digital computer system in accordance with claim 4, said serially connected integrand decade units 81-85 each comprising four flip-flops 261-264 respectively representing digits selectively addable to produce any digit from 1 through 9, each integrand decade unit 81-85 including a delay circuit 289 connected with said input 281 for responding to said input pulses to produce delayed pulses, and said serial connection circuit 266-275 comprising gates 266, 272 and 267, 271 for selectivEly applying said input and delayed pulses to said flip-flops 261-264, said integrand register being operable to respond to each input pulse and associated delayed pulse for shifting by one the count stored therein.

Claim 10

In a digital computer system in accordance with claim 4, said serially connected integrand decade units 81-85 each comprising four flip-flops 261-264 respectively representing digits selectively addable to produce any digit from 1 through 9, said serial connection circuit 266-275 being operable in a countdown mode to respond to each input pulse at said input 281 of said integrand register to reduce by one the count stored therein, means 312 associated with said serial connection circuit 266-275 for generating a borrow pulse when all of said flip-flops 261-264 are reset to represent a zero count, and means 305 connecting said integrand decade units 81-85 in series to apply a borrow pulse from each integrand decade unit to the input 281 of a succeeding integrand decade unit.

Claim 11

In a digital computer system in accordance with claim 4, said integrand decade units 81-85 each comprising four flip-flops 261, 262, 263, and 264 with a zero count being represented by a reset condition of all four of said flip-flops 261-264, an AND-gate 350 in each unit having five inputs 352, 307, 294, 309 and 311 and an output 351, means connecting one 352 of said inputs to the output 351 of the succeeding integrand decade unit of next higher significance, and means connecting the other four 307, 294, 309 and 311 of said five inputs to said four flip-flops 261-264 to develop an output from said gate 350 in response to concurrence of a reset condition of all four of said flip-flops 261-264 and a signal from the output 351 of the gate 350 of the succeeding integrand decade unit.

Claim 12

In a digital computer system, a. a pulse code unit 76 having noncarry outputs 145-148 and a carry output 151, and operable through a cycle of operation in response to application of 10 input pulses thereto for producing at the respective noncarry outputs 145-148 first, second, third and fourth series of noncarry pulses and for producing at the carry output 151 a carry pulse, said first series comprising five noncarry pulses coincident with the first, third, fifth, seventh and ninth of said 10 input pulses, said second series comprising two noncarry pulses coincident with the second and with the sixth of said 10 input pulses, said third series comprising one noncarry pulse coincident with the fourth of said 10 input pulses, said fourth series comprising one pulse coincident with the eighth of said 10 input pulses, and said carry pulse being coincident with the 10 th pulse of said 10 input pulses, b. a plurality of accumulator register units 71-75 connected in cascade and each comprising a decade counter 111-114 having an input 119 and an output 161, and having a bistable carry storage circuit 173 connected between the output 161 of each decade counter and the input 119 of the next succeeding decade counter, c. respective sets of first, second, third and fourth gates 122-125 connected with the respective noncarry outputs 145-148 of said pulse code unit 76 for respectively applying said first, second, third and fourth series of noncarry pulses to the input 119 of each of said decade counters, d. means 81-85 for selectively controlling said gates 122-125 in accordance with respective bits of a plural order coded decimal number weighted according to a 5, 2, 1'', 1 code so as to supply in parallel and simultaneously to the inputs 119 of the respective decade counters numbers of noncarry pulses from the pulse code unit in accordance with the respective digits of the plural order coded decimal number, during application of said 10 input pulses to said pulse code unit 76, e. said bistable carry storage circuits 173 being operable for storing a decade carry pulse from The decade counters 111-114 in response to a count of 10 of said decade counters 111-114, and f. said carry output 151 of said pulse code unit 76 being connected to a reset input of each of said bistable carry storage circuits 173 to cause an effective carry pulse to be transmitted from the bistable carry storage circuit 173 to the input 119 of the next decade counter, when a decade carry pulse has caused the previous setting of the bistable carry storage circuit, the effective carry pulses being generated in response to the carry pulse from the pulse code unit 76.

Claim 13

In a digital computer system, a. a pulse code unit 76 having noncarry outputs 145-148 and a carry output 151, and operable through a cycle of operation in response to application of 10 input pulses thereto for producing at the respective noncarry outputs 145-148 first, second, third and fourth series of noncarry pulses and for producing at the carry output 151 a carry pulse, said first series comprising five noncarry pulses coincident with the first, third, fifth, seventh and ninth of said 10 input pulses, said second series comprising two noncarry pulses coincident with the second and with the sixth of said 10 input pulses, said third series comprising one noncarry pulse coincident with the fourth of said 10 input pulses, said fourth series comprising one pulse coincident with the eighth of said 10 input pulses, and said carry pulse being coincident with the 10 th pulse of said 10 input pulses, b. a plurality of accumulator register units 71-75 connected in cascade and each comprising a decade counter 111-114 having an input 119 and an output 161, and having a bistable carry storage circuit 173 connected between the output 161 of each decade counter and the input 119 of the next succeeding decade counter, c. respective sets of first, second, third and fourth gates 122-125 connected with the respective noncarry outputs 145-148 of said pulse code unit 76 for respectively applying said first, second, third and fourth series of noncarry pulses to the input 119 of each of said decade counters, d. means 81-85 for selectively controlling said gates 122-125 in accordance with respective bits of a plural order coded decimal number weighted according to a 5, 2, 1'', 1 code so as to supply in parallel and simultaneously to the inputs 119 of the respective decade counters numbers of noncarry pulses from the pulse code unit in accordance with the respective digits of the plural order coded decimal number, during application of said 10 input pulses to said pulse code unit 76, e. said bistable carry storage circuits 173 being operable for storing a decade carry pulse from The decade counters 111-114 in response to a count of 10 of said decade counters 111-114, and f. said carry output 151 of said pulse code unit 76 being connected to a reset input of each of said bistable carry storage circuits 173 to cause an effective carry pulse to be transmitted from the bistable carry storage circuit 173 to the input 119 of the next decade counter, when a decade carry pulse has caused the previous setting of the bistable carry storage circuit, the effective carry pulses being generated in response to the carry pulse from the pulse code unit 76.

Claim 14

In a digital computer system in with claim 8, said means 81-85 for selectively controlling said gates 122-125 comprising an integrand register 81-85 having successive integrand decade counters each comprising four flip-flops 261-264 respectively representing digits in a 1, 1'', 2, 5 code, input means 281 for connection to a source of input pulses synchronized with the carry pulse from said carry output 151 of said pulse code unit 76, pulse-channelling means including gates 268-270 and 273-275 and 285 and 293 controlled by said flip-flops 261-264 for selectively triggering said flip-flops 261-264 in response to said input pulses for shifting by one the count stored in said integrand register 81-85 in response to each input pulse, and means 277, 278, 266-275 for selectively operating said pulse-channelling means in an addition mode wherein each input pulse increases the stored count by one and in subtraction mode wherein each input pulse decreases the stored count by one.

Claim 15

In a digital computer system in accordance with claim 8, said means 81-85 for selectively controlling said gates 122-125 comprising a series of integrand decade counters each comprising four flip-flops 261-264 respectively representing weights of 1, 1, 2 and 5, input means 281 for connection to a source of input pulses synchronized with the carry pulse from the carry output 151 of said pulse code unit 76, signal-channelling means including gates 268-270, 273-275, 285 and 293 controlled by said flip-flops 261-264 for selectively triggering said flip-flops 261-264 in response to input pulses for shifting by one the counts stored in said integrand register units 81-85 in response to each input pulse, and four output lines 132-135 respectively connected to the outputs of said four flip-flops 264, 263, 262 and 261 and connected to respective gates 122-125 of each of said sets of gates 122-125.