Method of reducing bit line to bit line coupled noise in a plated wire memory stack

Claim 2

In a plated wire memory stack comprising two arrays, each array including a plurality of parallel bit lines and a plurality of parallel word lines orthogonal to and inductively coupled to the bit lines, the bit lines of each array being arranged in groups of like numbers of contiguous bit lines, the method of reducing bit line to bit line coupled noise comprising: coupling alternate bit lines of each group of the first array to alternate bit lines of an associated group of the second array in a nontransposed manner; and, coupling the other-alternate bit lines of each group of the first array to the other-alternate bit lines of the aSsociated group of the second array in a transposed manner; for directing the current in contiguous bit lines to flow in like directions in said first array and in opposite directions in said second array.

Claim 3

The method of claim 1 further including: grouping the open ends of the alternate bit lines of two contiguous groups of bit lines of the first array for forming a first set of alternate bit lines including only the nontransposed-coupled alternate bit lines of the second array and defining a first bit of a plurality of multibit words; grouping the open ends of the other-alternate bit lines of said two contiguous groups of bit lines of the first array for forming a second set of other-alternate bit lines including only the transposed-coupled other-alternate bit lines of the second array and defining a second bit of said multibit words.

Claim 4

The method of claim 2 wherein said alternate bit lines are the even-ordered bit lines of each group; and said other-alternate bit lines are the odd-ordered bit lines of each group.

Claim 5

In a plated wire memory stack comprising two arrays, each array including a plurality of parallel, coplanar bit lines and a plurality of parallel word lines orthogonal to and inductively enveloping the bit lines, the bit lines arranged in groups of like numbers of contiguous, ordered bit lines, the method of reducing bit line to bit line coupled noise comprising: coupling each alternate-ordered bit line of each group of the first array to a separate like, alternate-ordered bit line of an associated group of the second array in a nontransposed manner; and, coupling each other-alternate-ordered bit line of each group of the first array to a separate like, other-alternate-ordered bit line of said associated group of the second array in a transposed manner; for directing the current in contiguous bit lines to flow in like directions in said first array and in opposite directions in said second array; grouping first ends of all of the alternate-ordered bit lines of two groups of bit lines of the first array for forming a first set of bit lines including all of the nontransposed alternate-ordered bit lines of the second array and defining the first bit of each of a plurality of multibit words; grouping first ends of all of the other-alternate-ordered bit lines of said two groups of bit lines of the first array for forming a second set of bit lines including all of the transposed other-alternate-ordered bit lines of the second array and defining the second bit of each of said plurality of multibit words; aligning the first and second bits of said multibit words along all of said word lines for forming as many multibit words along each of said word lines as said like numbers of contiguous bit lines in each of said groups of bit lines.

Claim 6

In a plated wire memory stack comprising two arrays, each array including a plurality of parallel, coplanar bit lines and a plurality of parallel word lines orthogonal to and inductively enveloping the bit lines, the bit lines arranged in groups of like numbers of contiguous, ordered bit lines, the method of reducing bit line to bit line coupled noise comprising: coupling each alternate-ordered bit line of each group of the first array to a separate like, alternate-ordered bit line of an associated group of the second array in a nontransposed manner; and, coupling each other-alternate-ordered bit line of each group of the first array to a separate like, other-alternate-ordered bit line of said associated group of the second array in a transposed manner; for directing the current in contiguous bit lines to flow in like directions in said first array and in opposite directions in said second array; grouping first ends of all of the alternate-ordered bit lines of two groups of bit lines of the first array for forming a first set of bit lines including all of the nontransposed alternate-ordered bit lines of the second array and defining the first bit of each of a plurality of multibit words; grouping first ends of all of the other-alternate-ordered bit lines of said two groups of bit lines of the first array for forming a second set of bit lines including all of the transposed other-alternate-ordered bit lines of the second array and defining the second bit of each of said plurality of multibit words; aligning the first and second bits of said multibit words along all of said word lines for forming as many multibit words along each of said word lines as said like numbers of contiguous bit lines in each of said groups of bit lines.

Claim 7

The method of claim 4 in which the alternate-ordered bit lines are the even-ordered bit lines and the other-alternate-ordered bit lines are the odd-ordered bit lines.

Claim 8

The method of claim 4 further including: coupling the first set of bit lines to a first line selector, and coupling the second set of bit lines to a second line selector.

Claim 9

In a plated wire memory stack comprising two arrays, each array including two planes, each plane including a plurality of parallel bit lines and a plurality of parallel word lines orthogonal to and inductively coupled to the bit lines, the bit lines arranged in groups of like numbers of contiguous, ordered bit lines, each group including a plurality of magnetizable material plated active lines and one half of the dummy lines being odd-ordered bit lines and the other half of the active lines and the other half of the dummy lines being even-ordered bit lines, the method of reducing bit line to bit line coupled noise comprising: intercoupling superposed, like-ordered bit lines of the first and second planes of the first array in a nontransposed manner; intercoupling superposed, like-ordered bit lines of the third and fourth planes of the second array in a nontransposed manner; intercoupling alternate like-ordered nonintercoupled ends of the bit lines of the second and third planes in a nontransposed manner; intercoupling the other-alternate like-ordered nonintercoupled ends of the bit lines of the second and fourth planes in a transposed manner; grouping the nonintercoupled ends of the bit lines of the first plane in a first set including only the intercoupled nontransposed bit lines of the first and second arrays, and grouping the nonintercoupled ends of the bit lines of the first plane in a second set including only the intercoupled transposed bit lines of the first and second arrays; coupling the first set of bit lines to a first active line, dummy line selector, and coupling the second set of bit lines to a second active line, dummy line selector.

Claim 10

In a plated wire memory stack comprising two arrays, each array including two planes, each plane including a plurality of parallel bit lines and a plurality of parallel word lines orthogonal to and inductively coupled to the bit lines, the bit lines arranged in groups of like numbers of contiguous, ordered bit lines, each group including a plurality of magnetizable material plated active lines and one half of the dummy lines being odd-ordered bit lines and the other half of the active lines and the other half of the dummy lines being even-ordered bit lines, the method of reducing bit line to bit line coupled noise comprising: intercoupling superposed, like-ordered bit lines of the first and second planes of the first array in a nontransposed manner; intercoupling superposed, like-ordered bit lines of the third and fourth planes of the second array in a nontransposed manner; intercoupling alternate like-ordered nonintercoupled ends of the bit lines of the second and third planes in a nontransposed manner; intercoupling the other-alternate like-ordered nonintercoupled ends of the bit lines of the second and fourth planes in a transposed manner; grouping the nonintercoupled ends of the bit lines of the first plane in a first set including only the intercoupled nontransposed bit lines of the first and second arrays, and grouping the nonintercoupled ends of the bit lines of the first plane in a second set including only the intercoupled transposed bit lines of the first and second arrays; coupling the first set of bit lines to a first active line, dummy line selector, and coupling the second set of bit lines to a second active line, dummy line selector.