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US3641405A Expired / Lapsed US ⏱️ 0.0 years remaining

Field-effect transistors with superior passivating films and method of making same

Assignee: General Electric Co
•
Filing: 1969-12-16
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Granted: 1972-02-08
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Expires: 1989-12-16
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Abstract

Abstract Improved semiconductor field-effect transistors have selfregistration and electrical insulation. Conductivity-modified, surface adjacent source and drain regions are formed by diffusing dopants through gate-oxide layer. One embodiment features a conducting gate electrode which is formed from a thin deposited film. In this embodiment a large region of opposite-conductivitytype semiconductor is formed by diffusion through both conducting and oxide films. Complementary ''''N-channel'''' and ''''P-channel'''' devices may be formed on the same substrate by combining two separate embodiments. In such devices the original conductivitytype semiconductor is the base for one FET, while the large conductivity-modified-type region is the base for the other FET. Such modules may be interconnected to form integrated circuits capable of performing a variety of logical functions.

Inventors

  • 👤 Dale M Brown
  • 👤 William E Engeler

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 10:21
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/692; H10P14/6921; H10P14/6922; H10P14/6923; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/858; H10D99/00; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6306; H10P14/6308; H10P14/6309; H10P14/6322; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/66; H10P14/662; H10P14/69215; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/141; H10P32/17; H10P32/171

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 38 words
The circuit array of claim 1 wherein a plurality of gate electrodes are disposed over said first thin region of said insulating layer, each of said gate electrodes being adjacent and partially defining respective source and drain regions.
Claim 2
Dependent Claim 35 words
The circuit array of claim 1 wherein a plurality of surface-adjacent portions of different conducting type semiconductor are formed upon the same substrate and source and drain regions therein are of opposite-conductivity type thereto, respectively.
Claim 3
Dependent Claim 20 words
The circuit array of claim 3 wherein said substrate is silicon and said surface-adjacent portion is a diffusion-modified portion thereof.
Claim 4
Dependent Claim 31 words
The circuit array of claim 1 wherein said gate electrode is enlarged at a portion thereof overlying said second thick region of said insulating layer to form a contact-making area thereof.
Claim 5
Dependent Claim 20 words
The circuit array of claim 1 wherein said insulating layer is silicon dioxide in both thick and thin regions thereof.
Claim 6
Dependent Claim 18 words
The circuit array of claim 6 wherein said insulating layer is a homogeneous thermally grown silicon dioxide layer.
Claim 7
Dependent Claim 39 words
The circuit array of claim 1 wherein said first thin region of said insulating layer is thermally grown silicon dioxide and said second thick diffusion-resistant region is a composite of said thermally grown layer and another layer disposed thereupon.
Claim 8
Dependent Claim 24 words
The circuit array of claim 8 wherein said other layer is formed from the group consisting of silicon dioxide, silicon nitride, and combinations thereof.

References Cited (Backward Citations)

US3461361A Cited
US3462657A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1975-02-07 1975-08-09 1976-02-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1979-02-07 1979-08-09 1980-02-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1983-02-07 1983-08-09 1984-02-08 $7700.00 Window Closed / Lapsed

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