Error correcting decoder utilizing estimator functions and decision circuit for bit-by-bit decoding

Claim 2

An error-correcting decoder circuit for decoding a received coded word made up of data bits and redundant bits, comprising storage means for storing the bits of said code word, means connected to said storage means and adapted to generate a plurality of estimator bits from selected bits of said coded word, said estimator bits being indicative of a certain one of said code bits, a decision circuit connected to receive said estimator bits and adapted to produce at the output thereof an output bit indicative of the majority of said estimator bits, said decision circuit being subject to having a meaningless output due to lack of a majority of said estimator bits, wherein the improvement comprises a tie detector circuit connected to said decision circuit and adapted to detect a lack of majority of said estimator bits, an output terminal for said decoder circuit, and switch means controlled by said tie detector circuit and adapted to connect said output terminal to said output of the decision circuit when majority output bits are being produced thereby, said switch means being further adapted under the control of said tie detector to connect said output terminal to said storage means for feeding said certain one of the data bits to said output terminal whenever said tie detector detects a lack of majority of said estimator bits.

Claim 3

A circuit as claimed in claim 1, in which said decision circuit comprises a plurality of translators respectively adapted to translate said estimator bits into positive polarity and negative polarity pulses or levels indicative of ''''1'''' and ''''0'''' estimator bits, an arithmetic adder connected to receive said positive and negative polarity pulses or levels and adapted to produce the arithmetic sum thereof, and a threshold circuit connected to the output of said arithmetic adder and adapted to produce said output bit indicative of the majority of said estimator bits, and in which said tie detector circuit comprises a null zone detector connected to receive said arithmetic sum from said arithmetic adder and adapted to produce a switch control signal in the event that the output of said arithmetic adder indicates less than a majority of said estimator bits, and means connecting said switch means to receive said switch control signal so as to be actuated thereby.

Claim 4

A circuit as claimed in claim 2, in which said switch means comprises a first AND circuit having an input connected to the output of said threshold circuit, an inverter circuit connected between the output of said null zone detector and another input of said first AND circuit, a second AND circuit having an input connected to said output of the null zone detector and having another input connected to said output of the null zone detector and having another input connected to receive said certain one of the data bits, and an OR circuit having inputs respectively connected to the outputs of said first and second AND circuits and an output connected to said decoder output terminal.

Claim 5

A circuit as claimed in claim 1, in which said estimator bits include said certain one of the code bits, and in which said decision circuit comprises a plurality of transLators respectively adapted to translate said estimator bits into positive polarity and negative polarity pulses or levels indicative of ''''1'''' and ''''0'''' estimator bits, a first arithmetic adder connected to receive said positive and negative polarity pulses or levels from said translators except for the translator of said certain one of the code bits and adapted to produce the arithmetic sum thereof, a threshold circuit connected to the output of said arithmetic adder and adapted to produce an output bit indicative of the majority of said estimator bits except for said certain one of the code bits, and a second arithmetic adder connected to receive the output of said first arithmetic adder and also the output of said translator for said certain one of the code bits, and in which said tie detector circuit comprises a null zone detector connected to receive the output of said second arithmetic adder and adapted to produce a switch control signal in the event that the output of said second arithmetic adder indicates less than a majority of said estimator bits, and means connecting said switch means to receive said switch control signal so as to be actuated thereby.

Claim 6

A circuit as claimed in claim 4, in which said switch means comprises a first AND circuit having an input connected to the output of said threshold circuit, an inverter circuit connected between the output of said null zone detector and another input of said first AND circuit, a second AND circuit having an input connected to said output of the null zone detector and having another input connected to receive said certain one of the data bits, and an OR circuit having inputs respectively connected to the outputs of said first and second AND circuits and an output connected to said decoder output terminal.