Tandem sampling controller using delayed operation of plural sampling gates

Claim 2

Tandem sampling controller apparatus comprising: first and second samplers, each having an output and a signal input and a sampling trigger input for producing at the output a sample pulse having an amplitude representative of the amplitude of a signal applied to the signal input at the time a sampling trigger signal is applied to the sampling trigger input thereof; first and second signal storing means connected respectively to the outputs of the first and second samplers for storing the amplitude of sample pulses between sampling times; sample trigger generating means connected to the sampling trigger input of the first sampler for applying sampling trigger signals thereto at selected sampling times; means connecting the signal input of the second sampler to receive the stored sample pulses from the first signal storing means; delay means connected to the sample trigger generating means for applying a sampling trigger signal to the sampling trigger input of the second sampler a predetermined time interval after each sampling trigger signal applied to the sampling trigger input of the first sampler; a utilization circuit including a signal-controlled oscillator for producing an output frequency representative of the amplitude of the stored signal received from the second signal storing means; and circuit means connected to the signal input of the first sampler for applying thereto as the signal to be sampled a signal which is representative of the output frequency from said oscillator for controlling sAid output frequency about a selected frequency value.

Claim 3

Tandem sampling controller apparatus as in claim 1 wherein: said circuit means includes a signal mixer having an input connected to receive the output frequency from said oscillator and having another input connected to receive an applied signal frequency and having an output connected to the signal input of the first sampler for applying thereto a modulation product of signal frequencies applied to the inputs of said signal mixer.

Claim 4

Tandem sampling controller apparatus comprising: first and second samplers, each having an output and a signal input and a sampling trigger input for producing at the output a sample pulse having an amplitude representative of the amplitude of a signal applied to the signal input at the time a sampling trigger signal is applied to the sampling trigger input thereof; first and second signal storing means connected respectively to the outputs of the first and second samplers for storing the amplitude of sample pulses between sampling times; circuit means connected to the signal input for applying thereto a signal to be sampled; sample trigger generating means connected to the sampling trigger input of the first sampler for applying sampling trigger signals thereto at selected sampling times; means connecting the signal input of the second sampler to receive the stored sample pulses from the first signal storing means; delay means connected to the sample trigger generating means for applying a sampling trigger signal to the sampling trigger input of the second sampler a predetermined time interval after each sampling trigger signal applied to the sampling trigger input of the first sampler; compensating means including a capacitor and an inverting amplifier having an input connected to receive sampling trigger signals from said delay means and an output connected through said capacitor to said second signal storing means for applying compensating signal thereto to decrease signal perturbations appearing at the second signal storing means; and a utilization circuit connected to respond to the stored signal received from the second signal storing means.

Claim 5

Tandem sampling controller apparatus comprising: first and second samplers, each having an output and a signal input and a sampling trigger input for producing at the output a sample pulse having an amplitude representative of the amplitude of a signal applied to the signal input at the time a sampling trigger signal is applied to the sampling trigger input thereof; first and second signal storing means connected respectively to the outputs of the first and second samplers for storing the amplitude of sample pulses between sampling times; circuit means connected to the signal input for applying thereto a signal to be sampled; sample trigger generating means connected to the sampling trigger input of the first sampler for applying sampling trigger signals thereto at selected sampling times; means connecting the signal input of the second sampler to receive the stored sample pulses from the first signal storing means; delay means connected to the sample trigger generating means for applying a sampling trigger signal to the sampling trigger input of the second sampler a predetermined time interval after each sampling trigger signal applied to the sampling trigger input of the first sampler; compensating means including a capacitor and an inverting amplifier having an input connected to receive sampling trigger signals from said delay means and an output connected through said capacitor to said second signal storing means for applying compensating signal thereto to decrease signal perturbations appearing at the second signal storing means; and a utilization circuit connected to respond to the stored signal received from the second signal storing means.