US3638124A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus utilizing a tree network for companding and coding an analog signal in a pcm system
Assignee: Telefonaktiebolaget LM Ericsson AB
•
Filing: 1968-12-30
•
Granted: 1972-01-25
•
Expires: 1988-12-30
Abstract
Abstract An arrangement for companding an analog signal in a pulse code modulation system, comprising a tree network having one input and a number of outputs each corresponding to a subrange of the amplitude range within which the analog signal falls. The branches of the tree network comprise amplifiers having different amplification, by means of which signals belonging to different subranges are given different amplification. The outputs of the tree network are connected to an addition circuit at the output of which an analog companded signal is obtained. The arrangement is also provided with digital outputs from which a digital value corresponding to the subrange of the analog signal is obtained.
Inventors
- 👤 Stig Gustaf Lindqvist
- 👤 Ilmar Valfeid Vaher
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:55
CPC Classifications
H; H04; H04B; H04B14/00; H04B14/02; H04B14/04; H04B14/046; H04B14/048; H03; H03M; H03M1/00; H03M1/12; H03M1/34; H03M1/38; H03M1/44
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
355 words
In a pulse code modulation system, an arrangement for companding an analog signal according to a companding curve consisting of a plurality of linear segments wherein the analog signal is divided iNto a number of subranges within which signals are differently amplified, said arrangement comprising: an input means including an input for receiving the analog signal and two outputs; a plurality of subnetworks, each of said subnetworks including an input and an output and further comprising a rectifier and an amplifier serially connected between said input and output thereof, the inputs of a first pair of said subnetworks being connected to said input means, the outputs of a first group of said subnetworks being connected to the inputs of pairs of said subnetworks whereby a binary tree network is formed with a plurality of outputs, the plurality of outputs of said tree network being the outputs of a second group of said subnetworks, the rectifiers in each pair of said subnetworks being oppositely polarized, each of the subnetworks of said first group further comprising a two-input subtracting circuit having a difference output, the first input of each subtracting circuit being connected to the output of the amplifier of the associated subnetwork, the difference output of each subtracting circuit being connected to the output of the associated subnetwork, a different reference voltage source connected to the other input of each of said subtracting circuits, the reference voltages being associated with the line segments of the companding curve, the amplifiers in each of said subnetworks having a different predetermined amplification factor; a signal addition circuit, said signal addition circuit including a plurality of inputs and an output for transmitting the analog sum of the signals received at said inputs, each of said inputs being connected to a different one of the outputs of the subnetworks of the second group; and output means connected to the output of said addition circuit whereby an analog signal received at said input means is modified in accordance with amplitude levels by the tree network of said subnetworks and said addition circuit and transmitted by said output means as a companded signal.
Claim 2
Dependent Claim
355 words
In a pulse code modulation system, an arrangement for companding an analog signal according to a companding curve consisting of a plurality of linear segments wherein the analog signal is divided iNto a number of subranges within which signals are differently amplified, said arrangement comprising: an input means including an input for receiving the analog signal and two outputs; a plurality of subnetworks, each of said subnetworks including an input and an output and further comprising a rectifier and an amplifier serially connected between said input and output thereof, the inputs of a first pair of said subnetworks being connected to said input means, the outputs of a first group of said subnetworks being connected to the inputs of pairs of said subnetworks whereby a binary tree network is formed with a plurality of outputs, the plurality of outputs of said tree network being the outputs of a second group of said subnetworks, the rectifiers in each pair of said subnetworks being oppositely polarized, each of the subnetworks of said first group further comprising a two-input subtracting circuit having a difference output, the first input of each subtracting circuit being connected to the output of the amplifier of the associated subnetwork, the difference output of each subtracting circuit being connected to the output of the associated subnetwork, a different reference voltage source connected to the other input of each of said subtracting circuits, the reference voltages being associated with the line segments of the companding curve, the amplifiers in each of said subnetworks having a different predetermined amplification factor; a signal addition circuit, said signal addition circuit including a plurality of inputs and an output for transmitting the analog sum of the signals received at said inputs, each of said inputs being connected to a different one of the outputs of the subnetworks of the second group; and output means connected to the output of said addition circuit whereby an analog signal received at said input means is modified in accordance with amplitude levels by the tree network of said subnetworks and said addition circuit and transmitted by said output means as a companded signal.
Claim 3
Dependent Claim
44 words
The arrangement of claim 1 and further comprising binary discriminator means connected to the outputs of the subnetworks of said first group for transmitting binary signals in accordance with the polarity of the signal transmitted by the difference outputs of the associated subtraction circuits.
Claim 4
Dependent Claim
55 words
The arrangement of claim 2 and further comprising a plurality of signal inverting means, each of said signal inverting means being connected between the output of every second subnetwork of said second group and the associated input of said addition circuit whereby the signals received at the inputs of said addition circuit alternate in polarity.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-01-24 | 1975-07-26 | 1976-01-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-01-24 | 1979-07-26 | 1980-01-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-01-24 | 1983-07-26 | 1984-01-25 | $7700.00 | Window Closed / Lapsed |