US3638007A
Expired / Lapsed
US
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Digital control simulator
Assignee: Individual
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Filing: 1969-08-05
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Granted: 1972-01-25
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Expires: 1989-08-05
Abstract
Abstract There is disclosed a simple inexpensive digital controller simulator for processing and modifying an analog input waveform to obtain a desired modification thereof empirically by controlling a set of calibrated potentiometer dials which represent coefficients of a signal equation that correspond to those coefficients used in programming a digital computer for process control to achieve the desired modification. This simulator stores sequential signal samples on capacitors and recalls the stored samples to merge together with the analog waveform modified samples which are controlled in amplitude by the calibrated potentiometers. A delay is simulated in the merged signals by sampling them over a further sequence of time intervals and storing in capacitors for selective access. The delayed signals are then processed in a holding circuit providing a continuous selection of hold between zero and first order. The resulting processed signals then may be used for control of a plant or process from which feedback signals may be derived for merger with the analog input waveform to produce a closed loop control system.
Inventors
- 👤 Herbert B Brooks
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 05:09
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/48; G06G7/66
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
338 words
Versatile and simplified control simulator apparatus for processing a plurality of parameters in mathematic expressions of a sampled digital data process, comprising in combination, input circuit means for developing a variable analog voltage of determinable magnitude at a first terminal, a first and second plurality of capacitors, each capacitor having a common terminal and a free terminal, means coupling, at known time intervals, each of said first plurality of capacitors at said first terminal for receiving and storing on respective capacitors the magnitude of said analog voltage at the sampling interval, means coupling said capacitors with said stored voltage magnitude thereon in sequence at a series of further terminals a, b...n, a plurality of detecting means respectively nondestructively sampling and reproducing said voltage magnitude of said capacitors at each of said further terminals a, b...n, a first set of potentiometers respectively calibrated in terms of one set of coefficients coupled with one potentiometer receiving from each of said detecting means the stored voltage magnitudes and providing output signals comprising selected portions of the signals stored by said capacitors and reproduced by said detecting means as a definable part of said variable analog voltage selectively determined by the potentiometer setting, circuit means including a second set of potentiometers respectively calibrated in terms of a further set of coefficients similarly coupled to provide an output analog voltage representing selected portions of signals stores on said capacitors and further connected to convey a selected portion of the voltage at said first terminal to an intermediate terminal, means coupling the second plurality of capacitors one at a time at said intermediate terminal in timed synchronism with the coupling of the first-mentioned plurality of capacitors to receive and store the voltage magnitude appearing thereat at the respective sampling intervals on the respective capacitors, and a holding circuit comprising switching means selectively coupled to receive the signals stored upon said further plurality of capacitors in a sequence producing an output analog signal representative of the stored voltage magnitude on a succession of the capacitors.
Claim 2
Dependent Claim
338 words
Versatile and simplified control simulator apparatus for processing a plurality of parameters in mathematic expressions of a sampled digital data process, comprising in combination, input circuit means for developing a variable analog voltage of determinable magnitude at a first terminal, a first and second plurality of capacitors, each capacitor having a common terminal and a free terminal, means coupling, at known time intervals, each of said first plurality of capacitors at said first terminal for receiving and storing on respective capacitors the magnitude of said analog voltage at the sampling interval, means coupling said capacitors with said stored voltage magnitude thereon in sequence at a series of further terminals a, b...n, a plurality of detecting means respectively nondestructively sampling and reproducing said voltage magnitude of said capacitors at each of said further terminals a, b...n, a first set of potentiometers respectively calibrated in terms of one set of coefficients coupled with one potentiometer receiving from each of said detecting means the stored voltage magnitudes and providing output signals comprising selected portions of the signals stored by said capacitors and reproduced by said detecting means as a definable part of said variable analog voltage selectively determined by the potentiometer setting, circuit means including a second set of potentiometers respectively calibrated in terms of a further set of coefficients similarly coupled to provide an output analog voltage representing selected portions of signals stores on said capacitors and further connected to convey a selected portion of the voltage at said first terminal to an intermediate terminal, means coupling the second plurality of capacitors one at a time at said intermediate terminal in timed synchronism with the coupling of the first-mentioned plurality of capacitors to receive and store the voltage magnitude appearing thereat at the respective sampling intervals on the respective capacitors, and a holding circuit comprising switching means selectively coupled to receive the signals stored upon said further plurality of capacitors in a sequence producing an output analog signal representative of the stored voltage magnitude on a succession of the capacitors.
Claim 3
Dependent Claim
41 words
Apparatus as defined in claim 1 including two operational amplifiers coupled to the input circuit means to produce therefrom signals of opposite polarity and switches connecting each potentiometer in said first set selectively to receive signals from either of said amplifiers.
Claim 4
Dependent Claim
42 words
Apparatus as defined in claim 1 including two operational amplifiers coupled to produce signals of opposite polarity at said intermediate teRminal, and switches connecting each potentiometer in said second set selectively to supply signals to either of said amplifiers for processing therein.
Claim 5
Dependent Claim
65 words
Apparatus as defined in claim 1 wherein said holding circuit comprises two switching means respectively coupled to sample different stored voltages on said second plurality of capacitors and each having a further storage capacitor storing these samples, and a holding operational differential amplifier coupled to said further storage capacitors to thereby produce a variable order hold signal at the output of said holding operational amplifier.
Claim 6
Dependent Claim
29 words
Apparatus as defined in claim 4 including an integrator circuit and calibrated potentiometer in the output of said holding operational amplifier to produce a fractional order hold signal derivative.
Claim 7
Dependent Claim
38 words
Apparatus as defined in claim 5 including operational amplifier means combining said fractional order hold signal derivative with a signal at one of said further storage capacitors in said holding circuit to produce a simulation analog output signal.
Claim 8
Dependent Claim
32 words
Apparatus as defined in claim 6 including means processing said simulation analog output signal and feeding back the resulting processed signal to comprise a portion of the voltage at said first terminal.
Claim 9
Dependent Claim
199 words
Control simulator apparatus for processing analog voltage signals comprising in combination, a set of capacitors, each capacitor having one terminal in common and a free terminal, means for presenting, in sequence at known time intervals, samples of an analog voltage to a plurality of storage capacitors in said set at a corresponding set of terminals, means coupling a selected subset of said capacitors to receive said analog signals in modified form in a filter simulator circuit comprising a set of manually variable controls defining at least one set of coefficients of a mathematical transfer function by modifying said analog signal voltage magnitudes, means deriving an intermediate voltage which is a function of the stored voltages on said capacitors modified by the setting of said variable controls, means coupling a further subset of said capacitors to receive and store timed samples of said intermediate voltage in a predetermined time sampling sequence synchronously related to said known time intervals, delay selection switching means selectively deriving a sequence of delayed signals stored on capacitors in said further subset, and hold circuit means processing simultaneously the signal derived from two different capacitors by said delay means to derive therefrom an analog output signal.
Claim 10
Dependent Claim
199 words
Control simulator apparatus for processing analog voltage signals comprising in combination, a set of capacitors, each capacitor having one terminal in common and a free terminal, means for presenting, in sequence at known time intervals, samples of an analog voltage to a plurality of storage capacitors in said set at a corresponding set of terminals, means coupling a selected subset of said capacitors to receive said analog signals in modified form in a filter simulator circuit comprising a set of manually variable controls defining at least one set of coefficients of a mathematical transfer function by modifying said analog signal voltage magnitudes, means deriving an intermediate voltage which is a function of the stored voltages on said capacitors modified by the setting of said variable controls, means coupling a further subset of said capacitors to receive and store timed samples of said intermediate voltage in a predetermined time sampling sequence synchronously related to said known time intervals, delay selection switching means selectively deriving a sequence of delayed signals stored on capacitors in said further subset, and hold circuit means processing simultaneously the signal derived from two different capacitors by said delay means to derive therefrom an analog output signal.
Claim 11
Dependent Claim
28 words
Apparatus as defined in claim 8 including means in said filter simulator circuit for selecting and combining signals of opposed polarities as modified by said set of controls.
Claim 12
Dependent Claim
25 words
Apparatus as defined in claim 8 wherein said hold circuit means comprises a series circuit combination of a sampling circuit and a hold storage capacitor.
Claim 13
Dependent Claim
54 words
Apparatus as defined in claim 10 wherein said series circuit combination includes an integrating circuit coupled to process the holding circuit signal and a potentiometer control for deriving from the integrating circuit a fractional order hold, to provide at different potentiometer control settings a continuously variable hold from zero order to the first order.
Claim 14
Dependent Claim
25 words
Apparatus as defined in claim 8 including a low input current DC amplifier coupled to sense the voltage of each of said plurality of capacitors.
Claim 15
Dependent Claim
95 words
Apparatus as defined in claim 12 wherein each said low input current DC amplifier comprises a low leakage field-effect transistor with an input electrode connected directly to its capacitor to sense the voltage thereon, resistive devices connected to the other electrodes of the transistor, a first potential source coupled to the electrodes through said resistive devices, a transistor amplifier connected to one of said electrodes having an output resistor connected with a second potential source higher than the first, and a variable resIstive connection between the other one of said electrodes to said output resistor.
Claim 16
Dependent Claim
162 words
In a digital controller simulator apparatus, comprising in combination, input circuit means developing an analog input signal as a varying magnitude voltage signal at a first terminal connection, means sampling said signal at a plurality of known sequential time intervals to produce discrete signal samples, means storing said discrete sampled signals for recall, means for selectively modifying said sampled signals as a function of a coefficient of a transfer function operable on said analog signal, means recalling and reproducing selected ones of said sampled signals, combining them with at least a portion of said analog signal and processing these to produce an intermediate signal, means for simulating delay comprising means for sampling and storing said intermediate signal at selected time intervals synchronized with the sampling time of said sampled signals including selection means for selecting different ones of the stored intermediate signals stored at the time intervals to simulate a delay from the sampling times of the corresponding said discrete signal samples.
Claim 17
Dependent Claim
162 words
In a digital controller simulator apparatus, comprising in combination, input circuit means developing an analog input signal as a varying magnitude voltage signal at a first terminal connection, means sampling said signal at a plurality of known sequential time intervals to produce discrete signal samples, means storing said discrete sampled signals for recall, means for selectively modifying said sampled signals as a function of a coefficient of a transfer function operable on said analog signal, means recalling and reproducing selected ones of said sampled signals, combining them with at least a portion of said analog signal and processing these to produce an intermediate signal, means for simulating delay comprising means for sampling and storing said intermediate signal at selected time intervals synchronized with the sampling time of said sampled signals including selection means for selecting different ones of the stored intermediate signals stored at the time intervals to simulate a delay from the sampling times of the corresponding said discrete signal samples.
Claim 18
Dependent Claim
16 words
The combination as defined in claim 14 including holding means responsive to said delayed intermediate signals.
Claim 19
Dependent Claim
64 words
The combination as defined in claim 14 wherein the means for storing said sampled and intermediate signals comprises a set of storage capacitors for holding an analog voltage signal sample magnitude and switching means for sequentially presenting capacitors in said set for access at a plurality of terminals coupled into said means for modifying and said means for recalling and reproducing the sampled signals.
Claim 20
Dependent Claim
259 words
Control apparatus for processing a plurality of parameters in mathematical expressions of a sampled digital data process, comprising in combination, input circuit means developing a variable analog voltage of determinable magnitude at a first terminal, a first plurality of capacitors, each having a common terminal and a free terminal, means presenting, at known time intervals, a sample of said analog voltage to each of said first plurality of capacitors at said terminal for receiving and storing said voltage magnitude samples in said capacitors, means connecting said capacitors in sequence to a series of further terminals a, b...n, a plurality of detecting means nondestructively sampling said voltage magnitude of said capacitors simultaneously at each of said further terminals a, b...n to reproduce the samples independently, a set of potentiometers respectively calibrated in terms of a set of coefficients with one such potentiometer coupled to each of said detecting means to provide selected portions of the signals on the corresponding ones of said capacitors, means mixing together selected signals from a plurality of potentiometers in said set, a further plurality of capacitors, each having a common terminal and a free terminal, means presenting the mixed together signals to said further plurality of capacitors in timed synchronism with the time intervals of the first-mentioned plurality of capacitors to store in the further plurality of capacitors a series of samples of the magnitude of said mixed together signals, and means selectively taking output signals from predetermined ones of said further plurality of capacitors to represent sampled data delayed by known increments of time.
Claim 21
Dependent Claim
259 words
Control apparatus for processing a plurality of parameters in mathematical expressions of a sampled digital data process, comprising in combination, input circuit means developing a variable analog voltage of determinable magnitude at a first terminal, a first plurality of capacitors, each having a common terminal and a free terminal, means presenting, at known time intervals, a sample of said analog voltage to each of said first plurality of capacitors at said terminal for receiving and storing said voltage magnitude samples in said capacitors, means connecting said capacitors in sequence to a series of further terminals a, b...n, a plurality of detecting means nondestructively sampling said voltage magnitude of said capacitors simultaneously at each of said further terminals a, b...n to reproduce the samples independently, a set of potentiometers respectively calibrated in terms of a set of coefficients with one such potentiometer coupled to each of said detecting means to provide selected portions of the signals on the corresponding ones of said capacitors, means mixing together selected signals from a plurality of potentiometers in said set, a further plurality of capacitors, each having a common terminal and a free terminal, means presenting the mixed together signals to said further plurality of capacitors in timed synchronism with the time intervals of the first-mentioned plurality of capacitors to store in the further plurality of capacitors a series of samples of the magnitude of said mixed together signals, and means selectively taking output signals from predetermined ones of said further plurality of capacitors to represent sampled data delayed by known increments of time.
Claim 22
Dependent Claim
27 words
Control apparatus as defined in claim 17 including a holding circuit with an integrator circuit functioning to produce an output analog signal from said last-mentioned output signals.
Claim 23
Dependent Claim
56 words
Control apparatus as defined in claim 18 wherein the holding circuit provides a variable-order hold including means processing the sampled data from two of said further plurality of capacitors in a corresponding pair of processing channels, means selectively varying the amplitude of signals in one channel and means summing together processed signals from the two channels.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-01-24 | 1975-07-26 | 1976-01-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-01-24 | 1979-07-26 | 1980-01-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-01-24 | 1983-07-26 | 1984-01-25 | $7700.00 | Window Closed / Lapsed |