Credit-accumulating arrangement

Claim 2

A credit-accumulating arrangement comprising: credit input means actuated by the establishment of credit to produce a credit pulse on an associated input line, said credit pulse being representative of the credit increments allocated to the established credit; a plurality of binary full adder circuits connected in series to produce a binary representation of accumulated credits, each of said full adder circuits having a pulse input, a feedback input, a carry input, a primary output, and a carry output; means connecting the carry output of each of said full adder circuits to the carry input of the next succeeding full adder circuit; switching means for simultaneously directing said credit pulse to the pulse inputs of selected ones of said full adder circuits; a plurality of delay flip-flop circuits, each of said flip-flop circuits connected to feed back a binary signal on the primary output of an associated one of said full adder circuits to the feedback input thereof; and toggle means connected to simultaneously energized all of said flip-flop circuits, after said full adder circuits have had time to respond to all input data, in order to simultaneously apply the binary signals on the primary outputs of all of said full adder circuits to the feedback inputs thereof to produce credit output signals, the primary output signals of said full adder circuits being utilized for accumulated credit information only at the time said toggle means are actuated.

Claim 3

A credit-accumulating arrangement as claimed in claim 1 and further comprising a plurality of OR gates, each OR gate connected to the pulse input of a corresponding one of said full adder circuits, said input line being connected to selected ones of said OR gates by said switching means.

Claim 4

A credit-accumulating arrangement as claimed in claim 1 wherein said toggle means comprises circuit elements adapted to simultaneously apply the trailing edge of said credit pulse to all of said flip-flop circuits to cause the binary signal on the primary output of each of said full adder circuits to be conveyed from an input of the associated flip-flop circuit to an output thereof.

Claim 5

A credit-accumulating arrangement as claimed in claim 1 and further comprising credit level detection means for determiNing the amount of credit accumulated in said full adder circuits.

Claim 6

A credit-accumulating arrangement as claimed in claim 1 and further comprising debit logic circuitry adapted to compare a credit accumulated in said full adder circuits with the price of an article selected to be vended and to initiate subtraction of the price of said article from the accumulated credit in said full adder circuits upon vending thereof.

Claim 7

An accumulating arrangement comprising: a plurality of binary full adder circuits connected in series, each of said full adder circuits having a pulse input, a feedback input, a carry input, a primary output, and a carry output; input means simultaneously applying input pulses to the pulse inputs of selected ones of said full adder circuits; a memory circuit connected between the primary output and feedback input of each of said full adder circuits; and transfer means adapted to simultaneously actuate all of said memory circuits after said full adder circuits have had time to respond to all input data to simultaneously apply the binary signal on the primary output of each of said full adder circuits to the feedback input thereof to produce credit output signals representative of the states of said full adder circuits only at the time said transfer means are actuated, whereby the input pulses applied to said full adder circuits are accumulated by essentially simultaneous operation of all full adder circuits to which input pulses are applied at a given time.

Claim 8

An accumulating arrangement comprising: a plurality of binary full adder circuits connected in series, each of said full adder circuits having a pulse input, a feedback input, a carry input, a primary output, and a carry output; input means simultaneously applying input pulses to the pulse inputs of selected ones of said full adder circuits; a memory circuit connected between the primary output and feedback input of each of said full adder circuits; and transfer means adapted to simultaneously actuate all of said memory circuits after said full adder circuits have had time to respond to all input data to simultaneously apply the binary signal on the primary output of each of said full adder circuits to the feedback input thereof to produce credit output signals representative of the states of said full adder circuits only at the time said transfer means are actuated, whereby the input pulses applied to said full adder circuits are accumulated by essentially simultaneous operation of all full adder circuits to which input pulses are applied at a given time.

Claim 9

An accumulating arrangement as claimed in claim 6 wherein each of said memory circuits comprises a flip-flop circuit having an input terminal connected to the primary output of the associated full adder circuit, an output terminal connected to the feedback input of the associated full adder circuit, and a toggle terminal connected to said transfer means.

Claim 10

An accumulating arrangement as claimed in claim 7 wherein said transfer means comprises circuit elements adapted to convert the trailing edge of each input pulse into a toggle signal which is simultaneously applied to the toggle terminal of each of said flip-flop circuit to transfer the binary signal on the input terminal thereof to the output terminal thereof.

Claim 11

An accumulating arrangement as claimed in claim 6 wherein the carry output of each of said full adder circuits, except for the last full adder circuit in said series of full adder circuits, is connected to the carry input of the next succeeding full adder circuit.

Claim 12

An accumulating arrangement as claimed in claim 9 and further comprising retaining means for maintaining said memory circuits in their existing condition upon production of a signal at the carry output of said last full adder circuit.

Claim 13

A credit-accumulating arrangement for use in a vending machine comprising: a plurality of binary full adder circuits connected in series, each of said full adder circuits having a pulse input, a feedback input, a carry input, a primary output, and a carry output, the carry output of all but the last of said full adder circuits being connected to the carry input of the next succeeding one of said full adder circuits; a plurality of coin switches, each coin switch adapted to produce a credit pulse on an associated input line in response to deposit of a corresponding coin in the vending machine; credit switching means connecting each of said input lines to the pulse inputs of selected ones of said full adder circuits to simultaneously apply a credit pulse appearing on an input line to all of the full adder circuits selected for that input line; a plurality of flip-flop circuits, each of said flip-flop circuits having an input terminal, an output terminal, and a toggle terminal, the input and output terminals of each of said flip-flop circuits connected, respectively, to the primary output in feedback input of an associated one of said full adder circuits; and toggle means producing a toggle pulse from The trailing edge of each credit pulse, each toggle pulse being simultaneously applied to the toggle terminal of all of said flip-flop circuits to simultaneously apply the signal at the primary output of each full adder circuit to the feedback input thereof to produce credit output signals representative of the state of said full adder circuits only at the time said toggle means is actuated.

Claim 14

A credit-accumulating arrangement for use in a vending machine comprising: a plurality of binary full adder circuits connected in series, each of said full adder circuits having a pulse input, a feedback input, a carry input, a primary output, and a carry output, the carry output of all but the last of said full adder circuits being connected to the carry input of the next succeeding one of said full adder circuits; a plurality of coin switches, each coin switch adapted to produce a credit pulse on an associated input line in response to deposit of a corresponding coin in the vending machine; credit switching means connecting each of said input lines to the pulse inputs of selected ones of said full adder circuits to simultaneously apply a credit pulse appearing on an input line to all of the full adder circuits selected for that input line; a plurality of flip-flop circuits, each of said flip-flop circuits having an input terminal, an output terminal, and a toggle terminal, the input and output terminals of each of said flip-flop circuits connected, respectively, to the primary output in feedback input of an associated one of said full adder circuits; and toggle means producing a toggle pulse from The trailing edge of each credit pulse, each toggle pulse being simultaneously applied to the toggle terminal of all of said flip-flop circuits to simultaneously apply the signal at the primary output of each full adder circuit to the feedback input thereof to produce credit output signals representative of the state of said full adder circuits only at the time said toggle means is actuated.

Claim 15

A credit-accumulating arrangement as claimed in claim 11 and further comprising: selecting switches providing pricing signals representative of the price of an item selected for vending; level detection means providing accumulated credit signals indicative of the credit accumulated in said full adder circuits; comparing means for producing a debit pulse in response to the application of a predetermined pricing signal and a predetermined accumulated credit signal thereto to initiate vending of a selected item; and debit switching means applying each debit pulse to selected ones of said full adder circuits to cause subtraction of credits corresponding to the price of the item being vended, whereby an item is vended and the price thereof is subtracted from the credits accumulated in said full adder circuits.

Claim 16

A credit-accumulating arrangement as claimed in claim 12 wherein said debit switching means connects the debit pulses to selected full adder circuits representing an arithmetical sum of credit increments which is the complement of the arithmetical sum of the credit increments allocated to the debit pulses in order to produce subtraction by complementary addition.

Claim 17

A credit-accumulating arrangement as claimed in claim 12 wherein said comparing means comprises a first AND gate.

Claim 18

A credit-accumulating arrangement as claimed in claim 12 wherein said level detection means comprises OR gates and AND gates appropriately connected to the output terminals of said flip-flop circuits.

Claim 19

A credit-accumulating arrangement as claimed in claim 12 wherein said credit switching means and said debit switching means each comprises a set of manually actuatable switches.

Claim 20

A credit-accumulating arrangement as claimed in claim 12 wherein said toggle means comprises a NAND gate receiving an input from each of said input lines and an inverting amplifier connected between the output of said NAND gate and the toggle terminals of said flip-flop circuits.

Claim 21

A credit-accumulating arrangement as claimed in claim 17 and further comprising: a set terminal on each of said flip-flop circuits; and a second AND gate receiving inputs from said comparing means, from said NAND gate, and from the carry output of the last full adder circuit in said series of full adder circuits, the output of said second AND gate being connected to the set terminals of said flip-flop circuits, whereby said flip-flop circuits are maintained in the maximum credit state upon production of a signal on the carry output of said last full adder circuit until a debit pulse is produced by said comparing means.

Claim 22

A credit-accumulating arrangement comprising: supply means for producing upon actuation thereof pulses representative of selected credit increments; a counter circuit having a plurality of stages; directing means connecting the pulses produced by said supply means to appropriate ones of said counter stages; a plurality of memory devices, each of said memory devices adapted upon actuation thereof to store a signal representing the state of an associated counter stage; and retaining means for maintaining each of said memory devices in its existing condition when said counter circuit registers a full count.

Claim 23

A credit-accumulating arrangement comprising: supply means for producing upon actuation thereof pulses representative of selected credit increments; a counter circuit having a plurality of stages; directing means connecting the pulses produced by said supply means to appropriate ones of said counter stages; a plurality of memory devices, each of said memory devices adapted upon actuation thereof to store a signal representing the state of an associated counter stage; and retaining means for maintaining each of said memory devices in its existing condition when said counter circuit registers a full count.

Claim 24

A credit-accumulating arrangement as claimed in claim 19 wherein: each of said counter circuit stages comprises a binary full adder circuit having a pulse input, a feedback input, a carry input, a primary output, and a carry output; and each of said memory devices comprises a flip-flop cirCuit having an input terminal, an output terminal, and a set terminal.

Claim 25

A credit-accumulating arrangement as claimed in claim 20 wherein said retaining means comprises an AND gate receiving inputs from said supply means and the carry output of the last full adder stage in said counter circuit, the output of said AND gate being connected to the set terminals of said flip-flop circuits, whereby said flip-flop circuits are maintained in the maximum credit state upon production of a signal on the carry output of said last full adder circuit.

Claim 26

A credit-accumulating arrangement as claimed in claim 21 and further comprising another input to said AND gate to render said AND gate inoperative to set the said flip-flop circuits upon the deduction of credit from the credit-accumulating arrangement.