Bowling split detector

Claim 2

A split detector comprising means responsive to the presence of a bowling ball in the alley pit to produce a succession of at least four delayed timing signals, means responsive to the first one of said timing signals to provide a respective pin signal for each pin standing of a first group of pins, said pin signals indicating by their occurrence that corresponding pins of said first group of pins are standing and indicating by their absence that corresponding pins of said first group of pins are down, means responsive to the second one of said timing signals to provide a respective second pin signal for each pin standing of a second group of pins, said second pin signals indicating by their absence that corresponding pins of said second group of pins are down, means responsive to the third of said timing signals to provide a respective third pin signal for each of a third group of pins, said third pin signals indicating by their occurrence that corresponding pins of said third group are standing and indicating by their absence that corresponding pins of said third group are down, means responsive to the fourth of said timing signals to provide a fourth pin signal to indicate that a predetermined pin is standing, absence of said fourth pin signal indicating that said predetermined pin is down, memory means to indicate through successive time signals after the first thereof whether any pin signals have been produced, additional memory means to indicate after each timing signal and through a next timing signal whether or not certain pin signals have been produced during the timing signal just previous to said next timing signal, means responsive to the occurrence of a signal indicating that the head pin is standing to prevent indication of a split, and means responsive to said pin signal and to the indications of each of said memory means to indicate a split when one occurs.

Claim 3

A bowling split indicator comprising means to provide a succession of timing signals, means responsive to a first timing signal to provide a pin pulse of a given length for each pin standing of a first group of pins during a first time period, means responsive to a second timing signal to provide a pin pulse of a length greater than said given length for each pin standing of a second group of pins during a second time period, means responsive to a third timing signal to provide a pin pulse of a length still greater than said greater length for each pin standing of a third group of pins during a third time period, means responsive to a fourth timing signal to provide a pin pulse of the greatest length to indicate that a furtheR pin is standing during a fourth time period, lack of occurrence of a pin pulse in each time period indicating that corresponding pins are down, means to provide memory signals at the end of each of the pin pulses of given length, of greater length and of still greater length, a plurality of flip-flop circuits each having at least one reset input terminal and at least one set input terminal and a negative output terminal and an affirmative output terminal, said flip-flop circuits providing one polarity of output at their negative terminals and the other polarity of output at the affirmative terminals in response to a pulse applied to the reset terminals and the opposite output potentials of their negative and affirmative terminals in response to a pulse applied to their set terminals, a plurality of AND circuits, said AND circuits each having a plurality of input terminals and an output terminal, each AND circuit providing an output at its output terminal only when pulses of the proper polarity are applied together to all its input terminals, means responsive to the first of said timing signals to provide a reset signal at the beginning of said first timing signal, means to apply said reset signals to a reset terminal of all of said flip-flop circuits, means to apply said pin pulses of the greatest length to a set input terminal of the first one of said flip-flop circuits, means to apply said memory signals at the end of said pin pulses of given length to a set terminal of said first flip-flop circuit and to a set terminal of a second of said flip-flop circuits, means to apply said memory signals at the end of said pin pulses of greater length to a set terminal of said first flip-flop circuit and also to a set terminal of a third of said flip-flop circuits, means to apply said memory signals at the end of said pin pulses of still greater length to a set terminal of said first flip-flop circuit and also to a set terminal of a fourth of said flip-flop circuits, means to apply said second, third and fourth timing signals to a reset terminal of said second, third and fourth flip-flop circuits, means to apply said pin pulses of given length and the negative output of said second flip-flop circuit to respective input terminals of a first AND circuit, means to apply said pin pulses of greater length and the negative outputs of said second and third flip-flop circuits to respective input terminals of a second AND circuit, means to apply said pin pulses of still greater length and the negative output of said third and fourth flip-flop circuits to respective input terminals of a third AND circuit, means to apply the affirmative output of said first flip-flop circuit, the outputs of said first, second and third AND circuits, and the second, third and fourth timing signals to input terminals of a fourth AND circuit, a plurality of inverter circuits each having an input and an output terminal and each of which provides an inverted version of the voltage applied to its input terminal at its output terminal, means to apply the pin pulses of given length, the pin pulses of greater length through one of said inverters, the pin pulses of still greater length and the second, third and fourth timing pulses to input terminals of a fifth AND circuit, means to apply said pin pulses of still greater length through another of said inverters, the pin pulses of greatest length, the pin pulses of greater length and the first timing pulse to respective input terminals of the sixth of said AND circuits, means to apply said pin pulses of said given length and said first timing signals to respective input terminals of a seventh of said AND circuits, means to apply the output of said seventh AND circuit to a set terminal of a fifth of said flip-flop circuits, means to apply the affirmative output of said fifth flip-flop circuit to a reset terminal of a sixth of said flip-flop cirCuits, and means to apply the outputs of said fourth, fifth and sixth AND circuits to set inputs of said sixth flip-flop circuits, whereby a predetermined voltage at the affirmative output terminal of said sixth flip-flop circuit shows that a split has occurred.

Claim 4

A bowling split indicator comprising means to provide a succession of timing signals, means responsive to a first timing signal to provide a pin pulse of a given length for each pin standing of a first group of pins during a first time period, means responsive to a second timing signal to provide a pin pulse of a length greater than said given length for each pin standing of a second group of pins during a second time period, means responsive to a third timing signal to provide a pin pulse of a length still greater than said greater length for each pin standing of a third group of pins during a third time period, means responsive to a fourth timing signal to provide a pin pulse of the greatest length to indicate that a furtheR pin is standing during a fourth time period, lack of occurrence of a pin pulse in each time period indicating that corresponding pins are down, means to provide memory signals at the end of each of the pin pulses of given length, of greater length and of still greater length, a plurality of flip-flop circuits each having at least one reset input terminal and at least one set input terminal and a negative output terminal and an affirmative output terminal, said flip-flop circuits providing one polarity of output at their negative terminals and the other polarity of output at the affirmative terminals in response to a pulse applied to the reset terminals and the opposite output potentials of their negative and affirmative terminals in response to a pulse applied to their set terminals, a plurality of AND circuits, said AND circuits each having a plurality of input terminals and an output terminal, each AND circuit providing an output at its output terminal only when pulses of the proper polarity are applied together to all its input terminals, means responsive to the first of said timing signals to provide a reset signal at the beginning of said first timing signal, means to apply said reset signals to a reset terminal of all of said flip-flop circuits, means to apply said pin pulses of the greatest length to a set input terminal of the first one of said flip-flop circuits, means to apply said memory signals at the end of said pin pulses of given length to a set terminal of said first flip-flop circuit and to a set terminal of a second of said flip-flop circuits, means to apply said memory signals at the end of said pin pulses of greater length to a set terminal of said first flip-flop circuit and also to a set terminal of a third of said flip-flop circuits, means to apply said memory signals at the end of said pin pulses of still greater length to a set terminal of said first flip-flop circuit and also to a set terminal of a fourth of said flip-flop circuits, means to apply said second, third and fourth timing signals to a reset terminal of said second, third and fourth flip-flop circuits, means to apply said pin pulses of given length and the negative output of said second flip-flop circuit to respective input terminals of a first AND circuit, means to apply said pin pulses of greater length and the negative outputs of said second and third flip-flop circuits to respective input terminals of a second AND circuit, means to apply said pin pulses of still greater length and the negative output of said third and fourth flip-flop circuits to respective input terminals of a third AND circuit, means to apply the affirmative output of said first flip-flop circuit, the outputs of said first, second and third AND circuits, and the second, third and fourth timing signals to input terminals of a fourth AND circuit, a plurality of inverter circuits each having an input and an output terminal and each of which provides an inverted version of the voltage applied to its input terminal at its output terminal, means to apply the pin pulses of given length, the pin pulses of greater length through one of said inverters, the pin pulses of still greater length and the second, third and fourth timing pulses to input terminals of a fifth AND circuit, means to apply said pin pulses of still greater length through another of said inverters, the pin pulses of greatest length, the pin pulses of greater length and the first timing pulse to respective input terminals of the sixth of said AND circuits, means to apply said pin pulses of said given length and said first timing signals to respective input terminals of a seventh of said AND circuits, means to apply the output of said seventh AND circuit to a set terminal of a fifth of said flip-flop circuits, means to apply the affirmative output of said fifth flip-flop circuit to a reset terminal of a sixth of said flip-flop cirCuits, and means to apply the outputs of said fourth, fifth and sixth AND circuits to set inputs of said sixth flip-flop circuits, whereby a predetermined voltage at the affirmative output terminal of said sixth flip-flop circuit shows that a split has occurred.

Claim 9

The apparatus of claim 4 wherein there are provided four separate timing signals and wherein each group includes a different number of pins.

Claim 10

The apparatus of claim 4 wherein said timing signal means further include means responsive to the presence of a bowling ball rolled past said array to produce said timing signals sequentially, means responsive to the first occurring of said timing signals to provide a reset signal, and means responsive to said reset signals to reset said apparatus.

Claim 11

The apparatus of claim 4 wherein said means for providing a plurality of pin signals including means responsive to said timing signals for scanning said array in a given sequence, each of said groups of pin signals being generated in response to a different, separate one of said timing signals, the pins in each of said groups being scanned substantially simultaneously in time coincidence with the corresponding timing signal.