US3633177A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data recorder with multiple input terminals
Assignee: DECISION DATA Inc A CORP OF
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Filing: 1969-09-15
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Granted: 1972-01-04
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Expires: 1989-09-15
Abstract
Abstract A key-to-magnetic tape recorder is provided with multiple keyboard units to enable a plurality of operators to simultaneously supply input message blocks to a magnetic tape unit for recordation on a single magnetic tape. Each keyboard unit has a buffer memory for accumulating a single message block. A multiplexer having a transfer memory with a capacity for storing a plurality of message blocks sequentially polls the keyboard terminals and when a terminal having a completed message is encountered, polling is interrupted and the terminal transmits the message to the transfer memory over a common transmitting cable. The tape unit has a single-message block buffer memory and when the unit indicates that it is ready to record the next message block, a block is transferred from the transfer memory to the tape buffer memory. All block sections of the transfer memory share a common set of input lines, a common set of output lines and a single set of accessing circuits. Just prior to the time each polling request is transmitted to the terminals, the multiplexer controls inspect for the presence of at least a single message in the transfer memory and a message demand indication from the tape unit. If both these requirements are present, the polling operation is inhibited and a message is transferred out of the transfer memory. In this way unloading of the transfer memory takes priority over loading and maximum message transfer efficiency is accomplished with minimum hardware. Error control means automatically operate upon detection of certain types of transmission errors to reject the message and to notify the keyboard terminal from which the erroneous message was transmitted. Display means are provided for indicating the terminal origin of each message stored in the transfer memory and the tape unit buffer memory.
Inventors
- 👤 Earl W Caldwell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 11:21
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/22; G06F11/00; G06F11/07; G06F11/16; G06F11/1608; G06F11/1612
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
228 words
In a data transfer system for channelling a message from any one of a plurality of message input terminals to a single-message processing station, the combination comprising: a transfer memory having a number of message storage sections less than the number of said input terminals, said memory having a single set of input lines common to all said sections, a single set of output lines common to all said sections and a single addressing circuit for addressing one said section at a time for both input and output operations; loading means for periodically transmitting polling requests to said terminals to initiate the transfer of a message from one of said terminals to said transfer memory; first status means for generating a first status signal indicative of the presence of at least one message in said transfer memory; demand means for generating a demand signal indicative of the requirement for a message at said processing station; unloading means for transferrinG a message from said transfer memory to said processing station, said unloading means including blocking means for inhibiting the operation of said loading means during operation of said unloading means; and control means for sampling the condition of said status means and said demand means just prior to the initiation of each said polling request and for actuating said unloading means in response to coincident status and demand signals.
Claim 2
Dependent Claim
228 words
In a data transfer system for channelling a message from any one of a plurality of message input terminals to a single-message processing station, the combination comprising: a transfer memory having a number of message storage sections less than the number of said input terminals, said memory having a single set of input lines common to all said sections, a single set of output lines common to all said sections and a single addressing circuit for addressing one said section at a time for both input and output operations; loading means for periodically transmitting polling requests to said terminals to initiate the transfer of a message from one of said terminals to said transfer memory; first status means for generating a first status signal indicative of the presence of at least one message in said transfer memory; demand means for generating a demand signal indicative of the requirement for a message at said processing station; unloading means for transferrinG a message from said transfer memory to said processing station, said unloading means including blocking means for inhibiting the operation of said loading means during operation of said unloading means; and control means for sampling the condition of said status means and said demand means just prior to the initiation of each said polling request and for actuating said unloading means in response to coincident status and demand signals.
Claim 3
Dependent Claim
51 words
The data transfer system set forth in claim 1, further comprising: second status means for generating a second status signal indicative of the nonavailability of an empty message storage section in said transfer memory; and means for inhibiting the operation of said loading means in response to said second status signal.
Claim 4
Dependent Claim
92 words
The data transfer system set forth in claim 1, further comprising: first error means for checking the accuracy of each message transfer from a terminal to said transfer memory, said first error means generating an OK signal upon completion of a successful transfer and a TEI signal upon detection of an unsuccessful transfer; lockout means at each said terminal for blocking the accumulation of further message data at said terminal during said message transfer operation; and release means at each said terminal responsive to said OK signal for disabling said lockout means.
Claim 5
Dependent Claim
24 words
The data transfer system set forth in claim 3, further comprising: means responsive to said TEI signal for initiating a retransfer of said message.
Claim 6
Dependent Claim
60 words
The data transfer system set forth in claim 4, further comprising: means included within said first error means for generating a BR signal upon detection of two successive unsuccessful message transfers from the same terminal; and means at said transferring terminal responsive to said BR signal for providing an alarm indication at said terminal and for actuating said release means.
Claim 7
Dependent Claim
85 words
The data transfer system set forth in claim 3 wherein said transfer memory further comprises: a gating circuit for each said message storage section for transmitting the outputs from said addressing circuit to said respective storage sections; a sequentially advanceable selection circuit having an output connected to control each of said gating circuits, said selection circuit outputs being supplied in a mutually exclusive manner; and means connecting said first error means to said selection circuit whereby each said OK signal switches the output state thereof.
Claim 8
Dependent Claim
64 words
The data transfer system set forth in claim 1 further comprising: error means for checking the accuracy of each message transfer from said transfer memory to said processing station, said error means generating a CHK signal upon completion of a successful transfer and a CHK signal upon detection of an unsuccessful transfer; and means responsive to said CHK signal for disabling said blocking means.
Claim 9
Dependent Claim
24 words
The data transfer system set forth in claim 7, further comprising: means responsive to said CHK signal for initiating a retransfer of said message.
Claim 10
Dependent Claim
52 words
The data transfer system set forth in claim 8, further comprising: means included within said error means for generating a TE2 signal upon detection of two successive unsuccessful message transfers from said transfer memory; and means responsive to said TE2 signal for providing an alarm indication and for disabling said blocking means.
Claim 11
Dependent Claim
84 words
The data transfer system set forth in claim 7 wherein said transfer memory further comprises: a gating circuit for each said message storage section for transmitting the outputs from said addressing circuit to said respective storage sections; a sequentially advanceable selection circuit having an output connected to control each of said gating circuits, said selection circuit outputs being supplied in a mutually exclusive manner; and means connecting said error means to said selection circuit whereby each said CHK signal sWitches the output state thereof.
Claim 12
Dependent Claim
194 words
In a data transfer system for channelling a message from any one of a plurality of message input terminals to a single-message processing station, the combination comprising: a transfer memory; means at each said input terminal for indicating when a complete message has been accumulated at said terminal; means responsive to said last-mentioned means for connecting said terminal to said transfer memory and for transferring said message to said transfer memory; means for transmitting a terminal identifying code with said message; blocking means for inhibiting the further accumulation of message data at said connected terminal during said transfer operation; means for disconnecting said terminal and disabling said blocking means upon completion of said transfer operation whereby said terminal is freed to accumulate further message data; means operable subsequent to said last-mentioned means for transferring said message from said transfer memory to said processing station; error means for checking the accuracy of said transfer from said transfer memory and for generating an alarm signal upon detection of an error; and means responsive to said alarm signal for enabling the indication of said error condition at the terminal identified by the identifying code accompanying said message.
Claim 13
Dependent Claim
194 words
In a data transfer system for channelling a message from any one of a plurality of message input terminals to a single-message processing station, the combination comprising: a transfer memory; means at each said input terminal for indicating when a complete message has been accumulated at said terminal; means responsive to said last-mentioned means for connecting said terminal to said transfer memory and for transferring said message to said transfer memory; means for transmitting a terminal identifying code with said message; blocking means for inhibiting the further accumulation of message data at said connected terminal during said transfer operation; means for disconnecting said terminal and disabling said blocking means upon completion of said transfer operation whereby said terminal is freed to accumulate further message data; means operable subsequent to said last-mentioned means for transferring said message from said transfer memory to said processing station; error means for checking the accuracy of said transfer from said transfer memory and for generating an alarm signal upon detection of an error; and means responsive to said alarm signal for enabling the indication of said error condition at the terminal identified by the identifying code accompanying said message.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-01-03 | 1975-07-05 | 1976-01-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-01-03 | 1979-07-05 | 1980-01-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-01-03 | 1983-07-05 | 1984-01-04 | $7700.00 | Window Closed / Lapsed |