Patent US4601514A successfully refreshed from Google Patents.
US3633045A
Expired / Lapsed
US
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Multiple level detector
Assignee: Nokia of America Corp
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Filing: 1970-01-21
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Granted: 1972-01-04
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Expires: 1990-01-21
Abstract
Abstract A solid-state dual limit detector circuit provides three outputs depending on whether an input signal is more positive than a positive limit, more negative than a negative limit, or between the two limits. The sampling, decision making, storage, and timing functions of the signal pulse reconstituting circuits of a PCM telephone repeater are combined in a single circuit by providing such a dual limit detector with momentary sampling capability and a lock-in feature to hold the detected indication for half a clock cycle. The two extreme outputs of the dual limit detector control a pair of saturated amplifiers whose outputs are coupled in opposite directions to an output transformer to produce the reconstituted PCM signal.
Inventors
- 👤 Frederik Nordling
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 00:20
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/20; H04L25/24; H04L25/242
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
105 words
A multiple level detector comprising: a. a plurality of transistors having their emitters directly connected together; b. a source of substantially constant current applied to the emitter-collector circuits of said transistors so that only the transistor with the largest base voltage conducts at any given time; c. input means connected to apply a varying input voltage to the base of at least one of said transistors, and a fixed voltage to the base of another of said transistors; and d. output means connected to the collector circuit of at least one of said transistors to produce a substantially constant output voltage whenever said transistor conducts.
Claim 2
Dependent Claim
105 words
A multiple level detector comprising: a. a plurality of transistors having their emitters directly connected together; b. a source of substantially constant current applied to the emitter-collector circuits of said transistors so that only the transistor with the largest base voltage conducts at any given time; c. input means connected to apply a varying input voltage to the base of at least one of said transistors, and a fixed voltage to the base of another of said transistors; and d. output means connected to the collector circuit of at least one of said transistors to produce a substantially constant output voltage whenever said transistor conducts.
Claim 3
Dependent Claim
65 words
The circuit of claim 1, in which there are three transistors, the base of the first of said transistors being operatively connected to said input signal source; the base of the second of said transistors being operatively connected to said input signal source and to a source of constant potential; and the base of the third of said transistors being maintained at a fixed potential.
Claim 4
Dependent Claim
66 words
The circuit of claim 2, in which said fixed potential is a ground potential about which the potential of said input signal varies; said second transistor is arranged to conduct when the magnitude of the input signal potential with respect to ground is smaller than a predetermined threshold value; and the magnitude of said constant potential with respect to ground is equal to said threshold value.
Claim 5
Dependent Claim
75 words
The circuit of claim 3, in which voltage dividing means are provided between said input, ground, and second transistor so as to apply only one-half of the potential of said input signal with respect to ground to the base of said second transistor, and in which means are also provided for applying a DC potential equal to one-half of said threshold value to the base of said second transistor concurrently with said halved input potential.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-01-03 | 1975-07-05 | 1976-01-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-01-03 | 1979-07-05 | 1980-01-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-01-03 | 1983-07-05 | 1984-01-04 | $7700.00 | Window Closed / Lapsed |