US3633014A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital equalizer in which tap adjusting signals are derived by modifying the signal code format
Assignee: AT&T Inc
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Filing: 1970-03-13
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Granted: 1972-01-04
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Expires: 1990-03-13
Abstract
Abstract An all digital multitap transversal filter equalizer system is disclosed in which a received data signal is sampled at a predetermined rate. Each sample of the data signal is converted into a 10-bit serial digital word. The 10-bit word is multiplied by a second digital word successively at each tap to provide data for composite output data words. It has been found that by converting the composite output data word into one''s complement format, error magnitude and error polarity signals can be derived for adaptive adjustment without additional equipment.
Inventors
- 👤 John Lemp Jr
- 👤 Howard Clarence Meadors Jr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 15:37
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/03; H04L25/03006; H04L25/03012; H04L25/03019; H04L25/03038
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
141 words
In combination: means responsive to a received quantized signal for providing a first multibit data signal having a sign indicative bit and magnitude indicative bits; means responsive to error signals applied thereto for providing a second multibit data signal having a sign indicative bit and magnitude indicative bits; a digital multiplier for multiplying said magnitude indicative bits of said first and second multibit data signals for providing a third multibit data signal; means responsive to an exclusive-OR combination of said sign indicative bit of said first multibit data signal and said sign indicative bit of said second multibit data signal for algebraically operating on said third multibit data signal to provide a fourth multibit data signal; and means for applying one bit of said fourth multibit data signal as an error polarity signal to said second multibit data signal providing means.
Claim 2
Dependent Claim
141 words
In combination: means responsive to a received quantized signal for providing a first multibit data signal having a sign indicative bit and magnitude indicative bits; means responsive to error signals applied thereto for providing a second multibit data signal having a sign indicative bit and magnitude indicative bits; a digital multiplier for multiplying said magnitude indicative bits of said first and second multibit data signals for providing a third multibit data signal; means responsive to an exclusive-OR combination of said sign indicative bit of said first multibit data signal and said sign indicative bit of said second multibit data signal for algebraically operating on said third multibit data signal to provide a fourth multibit data signal; and means for applying one bit of said fourth multibit data signal as an error polarity signal to said second multibit data signal providing means.
Claim 3
Dependent Claim
79 words
The combination as defined in claim 1 in which: said received quantized signal has 2N significant information levels, where N is any positive integer; said first multibit data signal contains (N + M) bits, where M is any positive integer; said one bit of said fourth multibit data signal constituting said error polarity signal is the (N + 1)st most significant, and said (N + 2)nd most significant bit and remaining bits of lesser significance together define error magnitude.
Claim 4
Dependent Claim
53 words
The combination as defined in claim 2 in which said second multibit data signal providing means includes: means responsive to the long-term average of the exclusive-OR combination of said (N + 1)st most significant bit and said sign indicative bit of said first multibit data signal for altering said second multibit data signal.
Claim 5
Dependent Claim
125 words
The combination defined in claim 2 in which said second multibit data signal providing means includes: means responsive to said bits in said fourth multibit data signal defining error magnitude and said signal magnitude indicative bits of said first multibit data signal for providing product bits; means for storing the sum of said product bits and bits applied thereto; means for providing an increment signal when said bits in said storing means represent a value greater than a predetermined value; and means responsive to said increment signal for altering said second multibit data signal in accordance with the exclusive-OR combination of said (N + 1)st most significant bit of said fourth multibit data signal and said sign indicative bit of said first multibit data signal.
Claim 6
Dependent Claim
52 words
The combination as defined in claim 1 also including: means for supplying a fifth multibit data signal; and said means for algebraically operating on said third multibit data signal includes: means for algebraically combining said fifth multibit data signal with said third multibit data signal thereby providing said fourth multibit data signal.
Claim 7
Dependent Claim
20 words
The combination as defined in claim 5 also including: a multistage shift register for storing said fourth multibit data signal.
Claim 8
Dependent Claim
52 words
The combination as defined in claim 6 also including: a sample and hold circuit for sampling and storing the bit representing error polarity from one stage of said multibit shift register; means for connecting sAid sample and hold circuit to said second multibit data signal providing means thereby applying a signal thereto.
Claim 9
Dependent Claim
105 words
The combination as defined in claim 1 in which said digital multiplier is a serial multiplier including: a AND-gate responsive to said magnitude indicative bits of said first and second multibit data signals for providing a partial product signal; a serial full adder for adding signals applied thereto to provide a sum signal; means for applying said partial product signal to said serial full adder; a shift register having an input and an output for recording said sum signal at said output and providing a delayed replica signal thereof at said output; and means for applying said delayed replica signal to said serial full adder.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-01-03 | 1975-07-05 | 1976-01-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-01-03 | 1979-07-05 | 1980-01-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-01-03 | 1983-07-05 | 1984-01-04 | $7700.00 | Window Closed / Lapsed |