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US3631473A Expired / Lapsed US ⏱️ 0.0 years remaining

Manually keyed pulse transmitter

Assignee: Toshiba Corp
•
Filing: 1969-09-02
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Granted: 1971-12-28
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Expires: 1989-09-02
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Abstract

Abstract A signalling device with a plurality of signal generating switches, a plurality of pulse generating circuits corresponding to the respective switches, are provided, as well as an encoder for encoding outputs from the pulse generating circuits to supply encoded signals to a receiving device. The signalling device applies the signal from one of the signal generating switches to the receiving device while one or more other switches are maintained in their operative condition.

Inventors

  • 👤 Akio Yakata
  • 👤 Kiyoshi Kubota

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 07:05
CPC Classifications
H; H04; H04Q; H04Q1/00; H04Q1/18; H04Q1/30; H04Q1/32; H04Q1/36; G; G06; G06F; G06F3/00; G06F3/01; G06F3/02; G06F3/023

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 279 words
A signalling device comprising a plurality of signal generating switches, a plurality of detecting circuits for detecting the operation of said switches, each including an amplifier corresponding to a respective one of said switches and an integrating circuit connected to the output of said amplifier, a plurality of pulse forming circuits corresponding to a respective one of said detecting circuits each including a differentiating circuit being connected to the output of said integrating circuit and producing output pulses having a pulse width shorter than the interval of operation of said signal generating switches in response to signals detected by said detecting circuits, an encoder for encoding the output pulse signals from said pulse forming circuits and applying to a receiving device said encoded signals from a signal generating switch even while one or more other signaL generating switches are maintained in their operative state, an OR circuit connected to receive said output pulse signals or said encoded signals, a delay circuit connected to delay the output signal from the OR circuit a predetermined time, a first AND circuit connected to receive the output signal from the delay circuit, a pulse generating circuit responsive to the output signal from said first AND circuit for generating a synchronizing signal, a time emitter circuit connected between an output terminal of said pulse generating circuit and an input terminal of said first AND circuit to control said pulse generating circuit such that until a predetermined time interval elapses after generation of one synchronizing signal, the generation of the next succeeding synchronizing signal is prevented and means to apply said synchronizing signal to said receiving device to control the reception of said encoded signals.
Claim 2
Dependent Claim 279 words
A signalling device comprising a plurality of signal generating switches, a plurality of detecting circuits for detecting the operation of said switches, each including an amplifier corresponding to a respective one of said switches and an integrating circuit connected to the output of said amplifier, a plurality of pulse forming circuits corresponding to a respective one of said detecting circuits each including a differentiating circuit being connected to the output of said integrating circuit and producing output pulses having a pulse width shorter than the interval of operation of said signal generating switches in response to signals detected by said detecting circuits, an encoder for encoding the output pulse signals from said pulse forming circuits and applying to a receiving device said encoded signals from a signal generating switch even while one or more other signaL generating switches are maintained in their operative state, an OR circuit connected to receive said output pulse signals or said encoded signals, a delay circuit connected to delay the output signal from the OR circuit a predetermined time, a first AND circuit connected to receive the output signal from the delay circuit, a pulse generating circuit responsive to the output signal from said first AND circuit for generating a synchronizing signal, a time emitter circuit connected between an output terminal of said pulse generating circuit and an input terminal of said first AND circuit to control said pulse generating circuit such that until a predetermined time interval elapses after generation of one synchronizing signal, the generation of the next succeeding synchronizing signal is prevented and means to apply said synchronizing signal to said receiving device to control the reception of said encoded signals.
Claim 3
Dependent Claim 51 words
The signalling device according to claim 1, wherein said first AND circuit further receives from said receiving device a phase inverted signal representing the signal receiving condition of said receiving device to cause said receiving device to receive said encoded signals only when it is set to receive said encoded signals.
Claim 4
Dependent Claim 85 words
The signalling device according to claim 1, further comprising a second AND circuit connected to receive the output signal from said OR circuit and a signal from said receiving device, said signal representing the signal receiving condition of said receiving device, and a memory element for storing the output signal from said second AND circuit to supply the output thereof to said first AND circuit to cause said receiving device to receive said encoded signals only when it is set to receive said encoded signals.
Claim 5
Dependent Claim 51 words
The signalling device according to claim 3 wherein said memory element is connected to a display or warning device which indicates or gives an alarm the fact that a signal generating switch is operated when said receiving device is not set to a condition under which it can receive encoded signals.

References Cited (Backward Citations)

US3293640A Cited
US3483553A Cited
US3466647A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1974-12-27 1975-06-28 1975-12-28 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1978-12-27 1979-06-28 1979-12-28 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1982-12-27 1983-06-28 1983-12-28 $7700.00 Window Closed / Lapsed

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