Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
386 words
An apparatus for converting analog signals into a digital representation comprising: an input for receiving an analog input signal and for receiving a reference voltage of the opposite polarity from said analog input signal; an integrating circuit for integrating analog signals applied thereto; detecting means to signal when the output signal of said integrating circuit reaches a predetermined level; a clock for generating clock signals; counting means for counting applied clock signals; and sequence control means, said sequence control means including; a sequencer adapted to output a plurality of control pulses, first switch means for connecting said analog input signal to said integrating circuit for a predetermined first interval, when commanded by a first control pulse, second switch means for connecting said reference signal of the opposite polarity from said analog input signal to the input of said integrating circuit during a second interval following said first interval, gate means for directing the clock signals generated by said clock to said counting means during said second interval until said detecting means signals that the output signal of said integrating circuit has reached said predetermined level to thereby register a first count in said counting means representing said analog input signal, a first digital logic means adapted to output a first command signal, third switch means adapted to receive said first command signal, said third switch means connecting said reference signal to said integrating circuit upon receiving said first command signal for a third time interval determined by said first count, fourth switch means for applying said analog input signal to said integrating circuit for a fourth time interval when said fourth switch means is actuated by a second control pulse, and wherein said fourth interval includes said third interval, and second digital logic means for actuating said second switch means whereby said reference signal is applied to said integrating circuit, said second digital logic means also actuating said gate means for directing said clock signals generated by said clock to said counting means during a fifth time interval until said detecting means signals that the input signal of said integrating circuit has reached said predetermined level to thereby register in said counting means a second count representing the difference between said analog input signal and the representation of said analog input signal by said first count.
Claim 2
Independent Claim
386 words
An apparatus for converting analog signals into a digital representation comprising: an input for receiving an analog input signal and for receiving a reference voltage of the opposite polarity from said analog input signal; an integrating circuit for integrating analog signals applied thereto; detecting means to signal when the output signal of said integrating circuit reaches a predetermined level; a clock for generating clock signals; counting means for counting applied clock signals; and sequence control means, said sequence control means including; a sequencer adapted to output a plurality of control pulses, first switch means for connecting said analog input signal to said integrating circuit for a predetermined first interval, when commanded by a first control pulse, second switch means for connecting said reference signal of the opposite polarity from said analog input signal to the input of said integrating circuit during a second interval following said first interval, gate means for directing the clock signals generated by said clock to said counting means during said second interval until said detecting means signals that the output signal of said integrating circuit has reached said predetermined level to thereby register a first count in said counting means representing said analog input signal, a first digital logic means adapted to output a first command signal, third switch means adapted to receive said first command signal, said third switch means connecting said reference signal to said integrating circuit upon receiving said first command signal for a third time interval determined by said first count, fourth switch means for applying said analog input signal to said integrating circuit for a fourth time interval when said fourth switch means is actuated by a second control pulse, and wherein said fourth interval includes said third interval, and second digital logic means for actuating said second switch means whereby said reference signal is applied to said integrating circuit, said second digital logic means also actuating said gate means for directing said clock signals generated by said clock to said counting means during a fifth time interval until said detecting means signals that the input signal of said integrating circuit has reached said predetermined level to thereby register in said counting means a second count representing the difference between said analog input signal and the representation of said analog input signal by said first count.
Claim 3
Dependent Claim
47 words
An apparatus as claimed in claim 1 further comprising: bias means; and fifth switch means for connecting said bias means to said integrating means during the predetermined first interval, said bias means providing a 1 1/2 -bit offset whereby up-counters may be used in said converter circuit.
Claim 4
Dependent Claim
171 words
The counting means of claim 1 comprising: a counter device for counting the clock pulses during the second and fifth time intervals; a first register for storing the first count in seven-bit form; a second register for storing the second count in seven-bit form, said second register including two stages wherein is contained the two most significant bits of the second count in complimentary form; and third digital logic means for supplying clock pulses to said two stages and said first register upon actuation by a third control pulse, said third digital logic means adapted to supply clock pulses until said two stages counting said clock pulses has reached a binary count of 11 such that the binary number in said first and second registers is a 12-bit digital equivalent of said analog input signal wherein the number stored in said first register represents the seven most significant bits of said digital equivalent and the number stored in said second register represents the five least significant bits of said digital equivalent.