Calculating machines with a constant function key

Claim 2

A calculating machine including an input register into which digits are entered from a digit keyboard by means of a number of pulses determined in accordance with which of the keys of the keyboard are depressed, an accumulator register into which numbers are entered from the input register, a constant key which controls the input register to retain the number in the input register, and means processing the retained input register number to affect a calculation with the number in the accumulator register.

Claim 3

A calculating machine according to claim 1, wherein the calculating machine includes means for entering a digit from the digit keyboard into a digit stage of one of said means operable by the constant key in one operating position to enter a digit from the keyboard into the input register and in the other operating position to enter the digit from the keyboard into the accumulator register.

Claim 4

A calculating machine including an input register and an accumulator register, each register having a plurality of digit stages, a digit keyboard, digit entering means for entering a digit determined in accordance with which of the keys of the digit keyboard is depressed into a digit stage of one of said registers and a constant function key switch having two operating conditions and means connecting the constant switch with the digit-entering means into a circuit so that when the key switch is in one operating condition digits are entered into the input register from the keyboard when the key switch is in the other operating condition digits cannot be entered into the input register from the keyboard.

Claim 5

A calculating machine including an input register and an accumulator register, each register having a plurality of digit stages, a digit keyboard, digit entering means for entering a digit determined in accordance with which of the keys of the digit keyboard is depressed into a digit stage of one of said registers and a constant function key switch having two operating conditions and means connecting the constant switch with the digit-entering means into a circuit so that when the key switch is in one operating condition digits are entered into the input register from the keyboard when the key switch is in the other operating condition digits cannot be entered into the input register from the keyboard.

Claim 6

A calculating machine according to claim 3, wherein the digit-entering means includes means for clearing a number entered in either said register connected to the entering means and connected to the key switch including circuits operating when he key switch is moved from its initial operating position to the alternative operating position and back to its initial operating position again while said entering means is entering a number into a register then the number entered into the register after the movement of the key switch will replace the number entered into the register before the movement of the key switch.

Claim 7

A calculating machine according to claim 3, wherein the digit-entering means includes register clearing means for clearing a digit from one of said registers, and control means for controlling the register clearing means and the register entry means comprising a master oscillator; an input decade wiTh 10 counter outputs and a shift output said decade being connected to the output of the master oscillator with means dividing the continuously generated oscillator pulses into a continuous sequence of trains of 10 pulses which appear on the 10 counter outputs respectively, each train of 10 pulses being separated from the next train of 10 pulses by a register shift pulse which appears on a shift output and means connecting the shift pulse to the input register and the accumulator register; a timer circuit having a number of count states equal to the number of digit stages in the the input register and the accumulator register, an input of the timer circuit connected to the output of the 10th pulse of the trains of 10 pulses from the input decade so that the 10th pulses cause the count states of the timer circuit to be energized in continuous sequence; a slip counter having a number of count states equal to the number of digit stages in the input register and the accumulator register, one of the count states having an output which is connected to an invertor circuit and having another of the count states energized after said one count state with an output which is connected to an invertor circuit; a function counter having a first output which is connected to an invertor circuit, a second output which is connected to the register clearing means, and a third output which is connected to the register digit entry means; a first gate whose output is connected to the input of the slip counter and whose inputs are connected to the output of the fifth pulse from the input decade, and first output of the timer circuit, the inverted other count state of the slip counter and the third output of the function counter respectively; a first bistable; a first set of gates whose output is connected to the input of the function counter the first set of gates including a first gate having inputs connected to the first output of the function counter, a second output of the timer circuit, the output of the first pulse from the input decade an output from the first bistable circuit, a time delay circuit and an input from the digit keyboard respectively, a second gate having inputs connected to the second output of the function counter, a third output of the timer circuit and the output of the 10th pulse from the input decade respectively, a third gate having inputs connected to the second output of the timer circuit, the inverted first output of the function counter circuit and a time delay circuit connected to the third output of the function counter circuit respectively, and a fourth gate having outputs connected to the second output of the function counter the second output of the timer circuit, the inverted one output of the slip counter and the output of the fifth pulse from the input decade respectively and a second set of gates whose output is connected to the input of the first bistable circuit, the second set of gates including a first gate having inputs connected to the first output of the function counter the first output of the timer circuit, the other output from the first bistable circuit, the output of the first pulse from the input decade and the inverted output from the digit keyboard respectively, and a second gate having inputs connected to the third output of the function counter the third output of the timer circuit, the output of the first pulse from the input decade and the one output of the first bistable circuit respectively; and means operable when the key on the digit keyboard corresponding to the first digit of a number is depressed and when the first output of the function counter is energized to program the first gate of the first set of gates to transmit a pulse to the function counter to energize the second output thereof so as to enable the register entry means and to enable the second gate of the second set of gates so as to energize the other output of the first bistable circuit, and to transmit by the third gate of the third set of gates after a time delay a pulse to the function counter to energize the first output thereof to energize the first gate of the second set of gates so as to transmit a pulse to energize the one output of the first bistable circuit; and means operable when the key corresponding to second and subsequent digits are depressed on the keyboard to repeat the program with the fourth gate of the second set of gates energized before the second gate of the second set of gates so that the register clearing means is not enabled.

Claim 8

A calculating machine according to claim 5, wherein the constant function key switch includes means when releasably held in the one operating condition to generate a signal of one voltage level along a line and when releasably held in the other operating condition to generate a signal of another voltage level along the line.

Claim 9

A calculating machine according to claim 6, wherein the input register and the accumulator register each include a shift register buffer connected to the register so as to form an endless loop for circulating the digits of the number stored in the register; and wherein the input register and the accumulator register each include a carry store including a first bistable circuit whose output is connected to the output of the respective buffer, which output is energized when a digit of predetermined value is stored in the shift register buffer; whereby, when a digit not of the predetermined value is circulated into the shift register buffer, the one output of the carry store first bistable is energized; and whereby when a digit of the predetermined value is circulated into the shift register buffer, the other output of the carry store bistable circuit is energized.

Claim 10

A calculating machine according to claim 7, wherein the register clearing means includes a first gate of a fourth set of gates having an output connected to the input of the shift register buffer of the input register having inputs connected to the second output of the function counter, the one output of the carry store first bistable circuit of the input register and the inverted output of the one operating condition of the constant function key switch respectively and a first gate of a fifth set of gates having an output connected to the input of the shift register buffer of the accumulator register having inputs connected to the second output of the function counter, the one output of the carry store first bistable circuit of the accumulator register, the output of the one operating condition of the constant function key switch and the inverted output of the second output of the timer circuit respectively; and wherein the register digit entry means includes a second gate of the fourth set of gates having inputs connected to the third output of the function counter, the trains of 10 pulses of the input decade the other count state of the slip counter, the output of the digit keyboard, the inverted output of one operating condition of the constant function key switch and the inverted first output of the timer circuit respectively, and a second gate of the fifth set of gates having inputs connected to the third output of the function counter, the other count state of the slip counter, the trains of 10 pulses of the input decade, the line of the digit keyboard, and the output of the one operating condition of the constant function key switch respectively; and means connecting the circuits so as when the constant key switch is held at the one operating condition, the first gate of the fourth set of gates clears the number in the input register and the first gate of the fifth set of gates enters a number into the input register; and when the constant key is held at the other operating condition, the second gate of the fourth set of gates clears the number in the accumulator register and the second gate of the fifth set of gates enters a number into the accumulator register.

Claim 11

A calculating machine according to claim 8, wherein the calcUlating machine further includes a means for entering a decimal point and a means for clearing a decimal point; and wherein the decimal point entering means includes a decimal point function key switch, a second bistable circuit, a first gate having an output connected to the second bistable circuit and having inputs connected to the first output of the function counter, the decimal point function key switch, the output of the 10th pulse from the input decade and one output of the second bistable circuit respectively, a third gate of the fourth set of gates, the third gate having input connected to the third output of the function counter, the first output of the timer circuit, the output of the 10th pulse from the input decade, the one output of the second bistable, the inverted output of the one operating condition of the constant function key switch and the inverted other count state of the slip counter respectively, a decimal counter for storing the decimal point count of the accumulator register, the decimal counter having an output when the decimal point count is zero, and a sixth set of gates having the output connected to the input of the decimal counter, the first gate of the sixth set of gates having inputs connected to the third output of the function counter, the first output of the timer circuit, the output of the 10th pulse from the input decade, the one output of the second bistable circuit, the output of the one operating condition of the constant function key switch and the inverted other count state of the slip counter respectively; and wherein the decimal point clearing means comprises the decimal point function key switch, the second bistable circuit, the first gate connected to the input of the second bistable circuit, the first gate of the fourth set of gates and a second gate of the sixth set of gates, the second gate having inputs connected to the second output of the function counter, the first output of the timer circuit, the inverted output of the decimal point decimal counter and the output of the one operating condition of the constant function key switch respectively; and control circuits operable when the decimal point function key switch is not operated to transmit a signal along the output thereof, the decimal point in the input register and the accumulator register before the entry of the first digit are cleared by the first gate of the fourth set of gates and the second gate of the sixth set of gates respectively, and decimal point pulses are added at the entry of each digit into the input register and the accumulator register respectively by the third gate of the fourth set of gates and the first gate of the sixth set of gates respectively; and when the decimal point function key switch is operated to transmit a signal along the output thereof, the entry of decimal point pulses into the input register and the accumulator register respectively are inhibited by the operation of the first gate connected to the second bistable so as to change the output of the second bistable so as to inhibit the third gate of the fourth set of gates and the first gate of the sixth set of gates.

Claim 12

A calculating machine according to claim 9, including number-correcting means comprising a second gate whose output is connected to the input of the slip counter and whose inputs are connected to the second output of the timer circuit the inverted one count state of the slip counter, the output of the one operating condition of the constant function key switch and the output of a time delay connected to the inverted output of the one operating condition of the constant function key switch respectively; a second gate whose output is connected to the input of the second bistable circuit and whose inputs are connected to the first output of the function counter circuit the output of the one operating condition of the constant function key switch and the output of a time delay connected to the inverted output of the one operating condition of the cOnstant function key switch respectively and the third gate of the first set of gates; and control means operable when during the entry of digits the constant key switch is moved from its initial operating position to the alternative operating position and back to its initial operating position, the second gate connected to the slip counter pulses the slip counter back to the position required for entry of a first digit, the third gate of the first set of gates the function counter so that the first output is energized and the second gate connected to the second bistable ensures that the one output of the second bistable circuit is energized so that the decimal point count is cleared at the entry of a first digit.

Claim 13

A calculating machine according to claim 10, wherein the calculating machine includes means for retaining the number stored in the input register, said retaining means comprising the second bistable circuit, the first gate connected to the input of the second bistable circuit and a fourth gate of the fourth set of gates, the fourth gate having inputs connected to the second output of the function counter, the one operating condition of the constant function key switch, the inverted second output of the timer circuit and the other output of the second bistable circuit respectively; and means operable when the constant function key switch is held in the other operating condition, the fourth gate of the fourth set of gates circulates the number stored in the input register so as to retain the circulated number in the input register.

Claim 14

A calculating machine according to claim 11, wherein the calculating machine includes a means for displaying the numbers entered into a register from the digit keyboard, the displaying means comprising a number tube display device, a first connection means connected from the carry store of the input register to the display device, a second connection means connected from the carry store of the accumulator register to the display device, a third bistable circuit having one output controlling the operation of the first connection means and another output controlling the operation of the second connection, and a seventh set of gates connected to the third bistable circuit, the first gate of the seventh set of gates having inputs connected to the third output of the function counter, the second output of the timer circuit, the output of the first pulse from the input decade, and the one output of the third bistable circuit respectively, and the second gate of the seventh set of gates having inputs connected to the third output of the function counter, the third output of the timer circuit, the output of the first pulse from the input decade, the one output from the third bistable circuit and the output of the one operating condition of the constant function key switch respectively; and means operable when the constant function key switch is held in the one operating condition so that the first gate of the seventh set of gates causes the third bistable circuit to enable the first connection means so that the number stored in input register is displayed on the number tube display device and when the constant key switch is held in the other operating condition, the second gate of the seventh set of gates causes the third bistable circuit to enable the second connection means so that the number stored in the accumulator register is displayed on the number tube display device.