US3628165A
Expired / Lapsed
US
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Digital frequency discriminator
Assignee: ANDERSON JACOBSON Inc
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Filing: 1968-09-19
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Granted: 1971-12-14
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Expires: 1988-09-19
Abstract
Abstract A frequency discriminator with a signal limiter and level detector for digital communication systems using frequency modulation is provided by an arrangement for effectively measuring the period of a frequency modulated signal. A counter sets and resets a first flip-flop in accordance with the frequency shift of the signal within a given range, and sets a second flip-flop for one cycle of the input signal each time the period of the signal is determined to be for a frequency outside that range. The limiter at the input of the discriminator employs an integrating capacitor to set the maximum level of the input signal as a function of the input signal amplitude, and the level detector, set for a predetermined acceptable signal level, is connected to that capacitor. A second integrating capacitor connected in parallel with the first through a blocking diode is provided with a large RC time constant as compared with that of the first integrating capacitor for a long turn-on time, as compared with the turnoff time for the level detector. The second flip-flop set by the discriminator removes an insignificant fixed charge from the first integrating capacitor each time it is set. The charge removal becomes significant only when its average rate exceeds a predetermined level.
Inventors
- 👤 William O Swan Jr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 09:01
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/10; H04L27/14; H04L27/156; H04L27/1563; H03; H03G; H03G11/00; H03G11/02
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
59 words
Apparatus as defined in claim 1 wherein said last-named means comprises: decoding means for generating an inhibit signal when said counter has reached a predetermined number greater than said maximum number during a given cycle: and means responsive to said inhibit signal for inhibiting operation of said counter during said given cycle, thereby preventing further pulses from being counted.
Claim 2
Dependent Claim
91 words
Apparatus as defined in claim 2 wherein said counter comprises a triggered JK flip-flop in said least significant stage, said JK flip-flop having a trigger input terminal, and J and K control terminals, said JK flip-flop further having said clock pulses applied to said trigger input terminal, a binary-1 signal applied to said J input terminal, and said decoding means comprises a NAND gate having its output terminal connected to said K input terminal, said NAND gate having each of its input terminals connected to a different stage of said counter.
Claim 3
Dependent Claim
134 words
In a frequency-shift digital communications receiver system having a utilization device the combination comprising: a counter; means for discriminating between two frequencies of an input signal by counting clock pulses with said counter; means for determining the number of pulses counted by said counter at the conclusion of a given cycle of said input signal; means responsive to said determining means for transmitting to said utilization device binary signals corresponding to said two frequencies as detected; means for limiting said input signal to a predetermined level; means connected to said limiting means for detecting when the level of said input signal falls below a predetermined peak-to-peak level; and means in response to said level detecting means for transmitting a signal to said utilization means indicating the input signal has fallen below said predetermined level.
Claim 4
Dependent Claim
58 words
The combination as defined in claim 4 wherein said limiting means responds to said input signal to set the level to which it will be limited as a function of the product of the input signal frequency and amplitude whereby a significant drop in the product may limit said input signal to a level below said predetermined level.
Claim 5
Dependent Claim
104 words
The combination as defined in claim 4 wherein said limiting means comprises: a first diode coupling said input signal to a source of fixed reference potential; an integrating capacitor; and a second diode connected in series with said integrating capacitor, the anode of one of said first and second diodes being connected to the cathode of the other, whereby an integrating capacitor is provided in parallel with said first and second series connected diodes; and a resistor in parallel with said capacitor, whereby said input signals is limited in voltage amplitude by the voltage to which said capacitor is charged at any given time.
Claim 6
Dependent Claim
58 words
The combination as defined in claim 6 wherein the RC time constant of said capacitor in parallel with said resistor is selected to provide a substantially constant charge across said capacitor at a level above said predetermined value for an input signal of a predetermined amplitude and a frequency in a range defined approximately by said two frequencies.
Claim 7
Dependent Claim
41 words
The combination as defined in claim 7 including means for removing a predetermined charge from said capacitor if the number of pulses counted during a given frequency determining cycle is representative of an input signal at a frequency outside said range.
Claim 8
Dependent Claim
59 words
The combination as defined in claim 8 wherein the charge removed during said given cycle is selected to be by itself insufficient to lower the level to which said input signal is to be limited with respect to said reference potential below said predetermined value, but sufficient when combined with charge removals during other cycles at a predetermined rate.
Claim 9
Dependent Claim
94 words
The combination as defined in claim 6 wherein said limiting means further includes a third branch in parallel with said integrating capacitor comprising a relatively large capacitor in series with a diode, said diode being poled to transfer a charge from said integrating capacitor to said large capacitor, and a resistor in parallel with said large capacitor, whereby said limiter is provided with a long turn-on time required to charge said integrating capacitor to a substantially constant level for an input signal of a frequency in a range defined approximately by said two frequencies.
Claim 10
Dependent Claim
50 words
The combination as defined in claim 10 wherein the RC time constant of said integrating capacitor and said resistor in parallel therewith is selected to provide a turnoff time significantly less than said turn-on time to discharge said integrating capacitor when said input signal is removed, or its amplitude drops.
Claim 11
Dependent Claim
43 words
The combination as defined in claim 11 wherein said integrating capacitor is significantly smaller than said large capacitor whereby said integrating capacitor may be rapidly recharged to said substantially constant level if the input signal is removed or its amplitude drops only momentarily.
Claim 12
Dependent Claim
25 words
The combination as defined in claim 12 wherein said large capacitor is greater than said integrating capacitor by a factor of about 10 to 100.
Claim 13
Dependent Claim
42 words
The combination as defined in claim 13 including means for removing a predetermined charge from said integrating capacitor if the number of pulses counted during a given frequency determining cycle is representative of an input signal at a frequency outside said range.
Claim 14
Dependent Claim
62 words
The combination as defined in claim 14 wherein the charge removed during said given cycle is selected to be by itself insufficient to lower the level to which said input signal is to be limited with respect to said reference potential below said predetermined value, but sufficient when combined with charge removals during other cycles at a predetermined average rate of removal.
Claim 15
Dependent Claim
35 words
The combination as defined in claim 15 including means for preventing said counter from counting additional clock pulses significantly beyond the number of clock pulses which should be counted for the two frequencies being discriminated.
Claim 16
Dependent Claim
54 words
The combination as defined in claim 16 wherein said counter is allowed to count pulses until it has counted a predetermined number, and wherein said means comprises: decoding means for determining when said counter has reached said predetermined number; and inhibiting means responsive to said decoding means for preventing further pulses from being counted.
Claim 17
Dependent Claim
127 words
The combination as defined in claim 17 wherein said counter comprises a plurality of cascaded stages for storing binary signals representing numbers, including a least significant stage for storing binary signals representing the least significant digits of numbers stored and a triggered JK flip-flop in said least significant stage, said JK flip-flop having a trigger flip-flop input terminal, and J and K control terminals, said JK flip-flop further having said clock pulses applied to said trigger input terminal, a binary-1 signal applied to said J input terminal, and said decoding means comprises a NAND gate having its output terminal connected to said K input terminal said NAND gate having each of its input terminals connected to a true output terminal of a different stage of said counter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-12-13 | 1975-06-14 | 1975-12-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-12-13 | 1979-06-14 | 1979-12-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-12-13 | 1983-06-14 | 1983-12-14 | $7700.00 | Window Closed / Lapsed |