US3628047A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Nondissipative power loss suppression circuit for transistor controlled power converters
Assignee: Northrop Grumman Space and Mission Systems Corp
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Filing: 1970-04-06
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Granted: 1971-12-14
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Expires: 1990-04-06
Abstract
Abstract A nondissipative power loss suppression circuit for a transistor controlled DC power converter of the type having a pair of positive and negative input terminals for connection to a source of DC voltage, a power converter inductor having primary and secondary windings, one end of the primary windings being connected to the positive input terminal, a transistor having a base connected to a transistor drive circuit for control of the transistor with turn-on and turnoff pulses, a collector conducted to the other end of the power converter inductor primary winding, and an emitter connected to the negative input terminal, and an output diode in series arrangement for providing a DC voltage output across the arrangement. The power loss suppression circuit consists of an energy absorbing circuit connected to the terminals and the power converter inductor for absorbing input voltage power during a turn-on pulse while said output diode recovers and for transferring excess absorbed power to the source when the diode recovers. Also provided is an energy storage circuit connected to the positive terminal and collector for storing power in the power converter inductor and the energy absorbing circuit during a turnoff pulse. An energy transfer circuit connected to the negative terminal and the energy storage circuit provides for the transfer of energy stored by the energy storage circuit to the source during a succeeding turn-on pulse.
Inventors
- 👤 Donald L Cronin
- 👤 John J Biess
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 21:46
CPC Classifications
H; H02; H02M; H02M1/00; H02M1/32; H02M1/34; H02M3/00; H02M3/22; H02M3/24; H02M3/28; H02M3/325; H02M3/335; H03; H03F; H03F3/00; H03F3/20; H03F3/21; H03F3/217; H02M1/346; Y; Y02; Y02B; Y02B70/00; Y02B70/10
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
346 words
A power loss suppression circuit for a transistor controlled DC power converter of the type having a pair of positive and negative input terminals for connection to a source of DC voltage, a power converter inductor having primary and secondary windings, one end of the primary winding being connected to the positive input terminal, a transistor having a base connected to a transistor drive circuit for control of the transistor with turn-on and turnoff pulses, a collector connected to the other end of the power converter inductor primary winding, and an emitter connected to the negative input terminal, and an output diode in series arrangement for providing a DC voltage output across the arrangement, said power loss suppression circuit comprising: energy absorbing means connected to the terminals and said power converter inductor for absorbing input voltage power during a turn-on pulse while said output diode recovers and for transferring excess absorbed power to the source when the diode recovers, said energy absorbing means comprising an inductor having primary and secondary windings, said primary winding having one end connected to the negative terminal and the other end connected to a first diode, said first diode connected to the positive terminal, said secondary winding being in series arrangement with the power converter inductor primary winding and having one end connected to the positive terminal; energy storage means connected to the positive terminal and the collector for storing power in said power converter inductor and said energy absorbing means during a turnoff pulse, said energy storage means comprising a first capacitor and a second diode in series arrangement, said series arrangement being connected to the positive terminal and the transistor collector; and energy transfer means connected to the negative terminal and said energy storage means for transferring energy stored by said energy storage means to the source during a succeeding turn-on pulse, said energy transfer means comprising a third inductor having a winding, and a diode connected in series arrangement with said third inductor wiNding, said series arrangement being connected to the negative terminal and said energy storage means.
Claim 2
Dependent Claim
346 words
A power loss suppression circuit for a transistor controlled DC power converter of the type having a pair of positive and negative input terminals for connection to a source of DC voltage, a power converter inductor having primary and secondary windings, one end of the primary winding being connected to the positive input terminal, a transistor having a base connected to a transistor drive circuit for control of the transistor with turn-on and turnoff pulses, a collector connected to the other end of the power converter inductor primary winding, and an emitter connected to the negative input terminal, and an output diode in series arrangement for providing a DC voltage output across the arrangement, said power loss suppression circuit comprising: energy absorbing means connected to the terminals and said power converter inductor for absorbing input voltage power during a turn-on pulse while said output diode recovers and for transferring excess absorbed power to the source when the diode recovers, said energy absorbing means comprising an inductor having primary and secondary windings, said primary winding having one end connected to the negative terminal and the other end connected to a first diode, said first diode connected to the positive terminal, said secondary winding being in series arrangement with the power converter inductor primary winding and having one end connected to the positive terminal; energy storage means connected to the positive terminal and the collector for storing power in said power converter inductor and said energy absorbing means during a turnoff pulse, said energy storage means comprising a first capacitor and a second diode in series arrangement, said series arrangement being connected to the positive terminal and the transistor collector; and energy transfer means connected to the negative terminal and said energy storage means for transferring energy stored by said energy storage means to the source during a succeeding turn-on pulse, said energy transfer means comprising a third inductor having a winding, and a diode connected in series arrangement with said third inductor wiNding, said series arrangement being connected to the negative terminal and said energy storage means.
Claim 3
Dependent Claim
205 words
A power loss suppression circuit comprising: a first input terminal receiving positive direct current voltage; a second input terminal receiving negative direct current voltage; a first inductor having primary and secondary windings; said first inductor primary winding connected in series with a first diode and the series combination shunted across said first and second terminals; a second inductor having primary and secondary windings; a first transistor having a base, emitter and collector terminals; said first inductor secondary winding, said second inductor primary winding and the collector-to-emitter path of said first transistor connected in series, and the series combination shunted across said first and second terminals; a second diode and first capacitor connected in series, the free end of said second diode connected to said first terminal and the free end of said first capacitor connected to the juncture of said second inductor primary winding and the collector of said first transistor; a third inductor having a single winding connected in series with a third diode, the combination shunted between said second terminal and the juncture of said second diode and first capacitor, and a fourth diode and a second capacitor connected in series and the combination shunted across the secondary winding of said second inductor.
Claim 4
Dependent Claim
205 words
A power loss suppression circuit comprising: a first input terminal receiving positive direct current voltage; a second input terminal receiving negative direct current voltage; a first inductor having primary and secondary windings; said first inductor primary winding connected in series with a first diode and the series combination shunted across said first and second terminals; a second inductor having primary and secondary windings; a first transistor having a base, emitter and collector terminals; said first inductor secondary winding, said second inductor primary winding and the collector-to-emitter path of said first transistor connected in series, and the series combination shunted across said first and second terminals; a second diode and first capacitor connected in series, the free end of said second diode connected to said first terminal and the free end of said first capacitor connected to the juncture of said second inductor primary winding and the collector of said first transistor; a third inductor having a single winding connected in series with a third diode, the combination shunted between said second terminal and the juncture of said second diode and first capacitor, and a fourth diode and a second capacitor connected in series and the combination shunted across the secondary winding of said second inductor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-12-13 | 1975-06-14 | 1975-12-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-12-13 | 1979-06-14 | 1979-12-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-12-13 | 1983-06-14 | 1983-12-14 | $7700.00 | Window Closed / Lapsed |