Double balanced gate circuit

Claim 2

A double balanced gate circuit comprising a first and second differential switching means fed by a third differential switching means and a current source, means for providing a reference signal and a quadrature signal, a first terminal means for application of one of said signals to a control means of said first and second differential switch, and a second terminal means for application of the other signal to a control means of said third differential switch, and an output means connected to said first and second switch for providing a gate circuit output proportional to the phase difference between said signals during each half cycle thereof, and an integrating means coupled to said output means for providing an amplitude envelope proportional to said output.

Claim 3

A gate circuit as claimed in claim 1 including a second gate circuit having a pair of differential switching means fed by another differential switching means, said second gate circuit having a first terminal means for application of a signal to a control means of its switch pair and a second terminal means for application of a signal to a control means of its other switching means, and one terminal means of said second gate circuit being coupled to one terminal means of the first gate circuit for application of one signal to both circuits.

Claim 4

A gate circuit as claimed in claim 1 wherein each of said switching means are transistor pairs, said transistor pairs having a current carrying element in common connection to provide a single branch of each switching means, the other current carrying element of each transistor pair providing a branch pair of each switching means, and the bases of said transistors providing a control means of each switching means; each of said control means being capable of diverting the current of said single branch through either of the other branches of its switch in accordance with a signal thereon; said switching means having said single branch of each of said first and second switching means coupled to one branch respectively of said branch pair of said third switching means, and said single branch of said third switching means coupled to said current source; and said gating circuit including an integrating means coupled to one set of complementary branches of said branch pairs of said first and second switching means so as to provide an output proportional to the combination of said first and second input signals.

Claim 5

A gate circuit as claimed in claim 3 including another integrating means coupled to the other set of complementary branches of said branch pairs of said first and second switching means so as to provide a double ended output.

Claim 6

A gate circuit as claimed in claim 3 wherein said first and second signals have the same frequency but are different in phase, and the amplitude of both signals exceed the switching threshold of said switching means so that the output of said gate circuit provides an amplitude envelope proportional to said difference in phase.

Claim 7

A gate circuit as claimed in claim 3 wherein said first and second signals are identical in frequency and one of said signals is an information bearing signal and said information bearing signal having an amplitude less than the threshold switching value of the switching means to which it is applied so that said integrating means provides an amplitude envelope proportional to that of said information signal.

Claim 8

A gate circuit as claimed in claim 3 wherein said first and second signals are different in frequency and one of said signals is an information bearing signal, and said information bearing signal having an amplitude less than the threshold switching value of the switching means to which it is applied so that said integrating means provides an amplitude envelope proportional to that of said information bearing signal and at a frequency which is a combination of both signal frequencies.

Claim 9

A gating circuit as claimed in claim 3 whErein said first, second, and third switching means are a first, second, and third transistor pair; each of said transistor pairs having a current carrying element in common connection to provide said single branch, the other current carrying element of each transistor pair providing said branch pairs; and the bases of each transistor pair providing said control means of each switch.

Claim 10

A gate circuit as claimed in claim 3 wherein said transistor pairs are NPN-transistors, each pair having a common emitter connection which provides said single branch, and said collectors provide said branch pair.

Claim 11

A gate circuit as claimed in claim 3 wherein a common connection of complementary branches of the branch pairs of said first and second switching means is provided by a common impurity region of complementary transistors of said first and second transistor pairs.

Claim 12

A gate circuit as claimed in claim 3 wherein the impurity profile and junction area of said first transistor pair equals those of said second so as to provide matching voltage drops therein, and the impurity profile and junction area of each transistor of said third pair are equal so as to provide matching voltage drops therein.