Photoelectric time delay lock

Claim 1

A photoelectric time delay apparatus for actuating an electrical device, comprising, in combination: an electrical power supply providing a supply voltage; an opaque key member including a body portion having a plurality of apertures intermediate the ends thereof; a photoelectric lock including a housing having a channel therein for the insertion of said key member; an electrical switch mounted in said housing, being coupled to said power supply and adapted to be actuated by said key to provide said supply voltage on a circuit buss; a light source mounted in said housing adjacent one side of said channel and coupled to said supply buss, being energized by said supply voltage when said key is inserted in said channel and transmitting light rays across said channel through said plurality of apertures; a first plurality of photodetector means mounted in said housing adjacent the other side of said channel, being positioned in selective registration with said opaque key member to be responsive to light transmitted through said plurality of apertures; first circuit means coupled to said first plurality of photodetector means providing a first-type output signal in the event all of said photodetector means are illuminated through said plurality of apertures; a second plurality of photodetector means mounted in said housing adjacent said other side of said channel, being positioned in selective registration with said opaque key member to be normally blocked from light emitted from said source by said body portion of said key member; second circuit means coupled to said second plurality of photodetector means providing another first-type output signal in the event all of said second photodetector means are blocked but an opposite-type output signal when said second photodetector means are illuminated from said source through said key member; logic circuit means coupled to said first and second plurality of photodetector means and providing a control signal output in response to the time coincidence of inputs of said first-type output signals therefrom, said logic circuit means comprising: (a) a first AND logic gate coupled to said first and second plurality of photodetector means; (b) a first time delay circuit, having a first selected time delay, coupled to the output of said first AND gate; (c) a second time delay circuit, having substantially the same selected time delay as said first time delay circuit, coupled to said circuit buss; (d) a second AND logic gate, coupled to said first and second time delay circuits, becoming operative in response to time coincident outputs therefrom To provide said control signal; (e) relay circuit means coupled to said second AND gate, becoming energized by said control signal and applying said actuating signal to said electrical device; (f) circuit interruptor means operated by said relay circuit means; (g) a third time delay circuit, having a time delay greater than said first time delay, coupled to said circuit interruptor means; and (h) a resistance-capacitance charging circuit including at least one capacitor coupled to said second time delay circuit, said capacitor being adapted to be charged through said third time delay circuit and said circuit interruptor means to render said second time delay circuit inoperative after a time delay greater than said first time delay when either said first or second plurality of photodetector means provides a mutually opposite-type logic output signal, said circuit interruptor means, however, disconnecting said third time delay circuit upon operation of said second AND gate thereby preventing said capacitor from charging.