US3626414A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Doppler processing apparatus and method
Assignee: Boeing North American Inc
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Filing: 1968-11-29
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Granted: 1971-12-07
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Expires: 1988-11-29
Abstract
Abstract In a doppler processor system including an inertial guidance platform and a coherent radar having an azimuthally scanning antenna, the scan rate of which is substantially constant over all portions of the scan region, computing means for computing the on-boresight doppler velocity Vfd and the time rate of change of the doppler velocity V fd whereby the use of function potentiometers mounted on the radar antenna gimbal system is avoided, and increased utilization is made of an onboard computer. Direction matrix conversion computing means, responsive to said radar and to said inertial platform, provides a first and second output corresponding to a respective one of a preselected derivative of the doppler velocity and the product sEANVzRAD, where: SEAN sine of the antenna elevation angle VzRAD platform velocity resolved in the coordinates of the radar system. A first analog integrator responsive to said first output of the computing means provides a signal indicative of V fd; and signal combining means having a first and second input, responsive to a respective one of said second output of the computing means and to the double integral with respect to time of the first output of the computing means, provides a signal indicative of Vfd.
Inventors
- 👤 Jacob E Valstar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 10:48
CPC Classifications
G; G01; G01S; G01S7/00; G01S7/02; G01S7/28; G01S7/285; G01S7/295
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
188 words
In a doppler processor system including an inertial guidance platform and a coherent radar having an azimuthally scanning antenna, the scan rate of which is substantially constant over all portions of the scan region, means for computing the onboresight doppler velocity Vfd and the time rate of change of the doppler velocity V fd and comprising direction matrix conversion computing means responsive to said radar and to said inertial platform for providing a first and second output corresponding to a respective one of a preselected derivative of the doppler velocity and the product sEANVzRAD, where: sEAN sine of the antenna elevation angle in the coordinates of the radar system; VzRAD platform velocity resolved in the coordinates of the radar system; a first analog integrator responsive to said first output of said computing means for providing a signal indicative of V fd; and signal combining means having a first and second input responsive to a respective one of said second output of said computing means and to a preselected integral with respect to time of said first output of said computing means for providing a signal indicative of Vfd.
Claim 2
Dependent Claim
188 words
In a doppler processor system including an inertial guidance platform and a coherent radar having an azimuthally scanning antenna, the scan rate of which is substantially constant over all portions of the scan region, means for computing the onboresight doppler velocity Vfd and the time rate of change of the doppler velocity V fd and comprising direction matrix conversion computing means responsive to said radar and to said inertial platform for providing a first and second output corresponding to a respective one of a preselected derivative of the doppler velocity and the product sEANVzRAD, where: sEAN sine of the antenna elevation angle in the coordinates of the radar system; VzRAD platform velocity resolved in the coordinates of the radar system; a first analog integrator responsive to said first output of said computing means for providing a signal indicative of V fd; and signal combining means having a first and second input responsive to a respective one of said second output of said computing means and to a preselected integral with respect to time of said first output of said computing means for providing a signal indicative of Vfd.
Claim 3
Dependent Claim
16 words
The device of claim 1 in which said signal combining means includes said first analog integrator.
Claim 4
Dependent Claim
39 words
The device of claim 1 in which said signal combining means includes a second analog integrator responsively coupled to an output of said first analog integrator for generating said preselected integral of said first output of said integrating means.
Claim 5
Dependent Claim
81 words
The device of claim 1 in which said signal combining means comprises a second analog integrator responsively coupled to an output of said first integrator; analog means responsive to an output of said second integrator and to said second output of said cOmputing means for providing an output indicative of the analog sum thereof; and a first low-pass filter responsive to an output of said summing means and having a cutoff frequency not exceeding a sampling rate of said computing means.
Claim 6
Dependent Claim
73 words
The device of claim 1 in which said computing means further provides a third and fourth periodically sampled output corresponding to a respective one of V fd and the sum (Vfd+sEANVzRAD) of Vfd and said product sEANVzRAD, said third output of said computing means being coupled with said output of said first analog integrator, and said fourth output of said computing means being coupled to said second input of said signal combining means.
Claim 7
Dependent Claim
117 words
The device of claim 1 in which said computing means further provides a third and fourth periodically sampled output corresponding to a respective one of V fd and the sum (Vfd+sEANVzRAD) of Vfd and said product sEANVzRAD, said third output of said computing means being coupled with said output of said first analog integrator, and said fourth output of said computing means being coupled to said second input of said signal combining means, and in which there is provided a first and second low-pass filter respectively responsive to a respective output of said signal combining means and said first analog integrator, each said filter having a cutoff frequency not exceeding a sampling rate of said computing means.
Claim 8
Dependent Claim
118 words
The device of claim 1 in which said computing means further provides a periodically sampled third output corresponding to the sum (Vfd+sEANVzRAD) of the doppler velocity Vfd and said product sEANVzRAD, said third output being coupled with the output of said first analog integrator, and in which there is further provided a second analog integrator responsive to said coupled third output of said computing means and having an output coupled with said first output of said computing means; and a first and second low-pass filter respectively coupled to a respective output of said signal combining means and said second integrator, each said filter having a cutoff frequency not in excess of the sampling rate of said computing means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-12-06 | 1975-06-07 | 1975-12-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-12-06 | 1979-06-07 | 1979-12-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-12-06 | 1983-06-07 | 1983-12-07 | $7700.00 | Window Closed / Lapsed |