Automatic baud synchronizer

Claim 2

An automatic baud synchronizer compatible with multilevel coded data formats for sensing the optimum sampling time in an analog-to-digital converter in the receiver of a synchronous data communication system comprising means responsive to a received analog data waveform for generating a sampling pulse train of repetition rate equal to the transmitted data rate, and means responsive to the time of occurrence of the zero slope points of the received analog data waveform relative to the sampling pulse tRain for synchronizing the sampling pulse train with the average time of occurrence of the zero slope points, the use of the zero slope points adapting the baud synchronizer compatible with multilevel coded data formats having an arbitrary number of symbol levels.

Claim 3

The automatic baud synchronizer set forth in claim 1 wherein said sampling pulse train synchronizing means comprises a zero-slope detector circuit responsive only to the received analog data waveform for detecting the points of zero slope of the received analog data waveform, output of said zero-slope detector being recurrent pulses each occurring at the time of zero slope of the received analog data waveform and of duration directly proportional to the duration of the corresponding zero slope.

Claim 4

The automatic baud synchronizer set forth in claim 1 wherein said sampling pulse train generating means comprises a clock generator phase-locked with the transmitted data rate for generating a clock pulse train of repetition rate equal to a particular multiple of the transmitted data rate, and means in communication with the outputs of said clock generator and said sample pulse train synchronizing means for dividing the repetition rate of the clock generator pulse output by the particular multiple to obtain the sampling pulse train of repetition rate equal to the transmitted data rate.

Claim 5

The automatic baud synchronizer set forth in claim 1 and further comprising an analog-to-digital converter circuit comprising a first input supplied with the received analog data waveform, a second input in communication with the output of said sampling pulse train synchronizing means, and a first output of said converter providing the received analog data in serial binary logic form.

Claim 6

The automatic baud synchronizer set forth in claim 4 wherein said sampling pulse train synchronizing means comprises a zero-slope detector circuit responsive only to the received analog data waveform for detecting the points of zero slope of the received analog data waveform, output of said zero-slope detector being recurrent pulses each occurring at the time of zero slope of the received analog data waveform and of duration directly proportional to the duration of the corresponding zero slope.

Claim 7

The automatic baud synchronizer set forth in claim 5 wherein said sampling pulse train generating means comprises a clock generator phase-locked with the transmitted data rate for generating a clock pulse train of repetition rate equal to a particular multiple of the transmitted data rate, and means in communication with the output of said clock generator for dividing the repetition rate of the clock clock generator pulse output by the particular multiple to obtain the sampling pulse train of repetition rate equal to the transmitted data rate.

Claim 8

The automatic baud synchronizer set forth in claim 6 wherein said sampling pulse train synchronizing means further comprises means connected to a second output of said converter for generating a square waveform pulse train of repetition rate equal to the repetition rate of the sampling pulse train, the positive-to-negative transition of the square wave pulses being phase-locked with the average time of occurrence of the zero-slope detector output pulses during the optimum sampling time wherein the sampling pulse train is synchronized with the average time of occurrence of the zero slope points of the received analog data waveform.

Claim 9

The automatic baud synchronizer set forth in claim 7 wherein said sampling pulse train synchronizing means further comprises a binary logic up-down counter having a first input in communication with the outputs of said clock generator and said zero-slope detector, a second input connected to the output of said square waveform generating means wherein the square waveform controls the count direction of said counter, said counter provided with an overflow output and an underflow output.

Claim 10

The automatic baUd synchronizer set forth in claim 8 wherein said sampling pulse train synchronizing means further comprises a one-shot multivibrator connected to the output of said zero-slope detector for generating equal duration pulses in synchronism with the leading edges of the recurrent pulses generated in said zero-slope detector, and a NAND logic gate circuit having a first input connected to the output of said one-shot multivibrator and a second input connected to the output of said clock generator, the output of said NAND logic gate circuit connected to the first input of said counter whereby said counter increases its count by one each time said NAND logic gate circuit passes one clock pulse to said counter during the high-state output of said square waveform generating means and conversely decreases its count by one when the square waveform generating means output is at its low state.

Claim 11

The automatic baud synchronizer set forth in claim 9 wherein said sampling pulse train synchronizing means further comprises a digital phase-shift circuit having first inputs in communication with the overflow and underflow outputs of said counter and second inputs in communication with the output of said clock generator, said digital phase-shift circuit adapted to add a single clock pulse to said clock generator pulse output repetition rate dividing means each time said counter supplies an overflow pulse and conversely inhibit a single clock pulse in response to an underflow pulse supplied from said counter, the net effect of the added or inhibited clock pulses being to move the positive-to-negative transition of the square wave generated by the square waveform generating means in the direction of the average time of occurrence of the zero slope point of the received analog data waveform.

Claim 12

The automatic baud synchronizer set forth in claim 10 wherein said sampling pulse train synchronizing means further comprises an adaptive threshold circuit having inputs connected to the overflow and underflow outputs of said counter and outputs connected to said digital phase-shift circuit for preventing oscillation in the loop comprising said counter, digital phase-shift circuit, clock generator pulse output repetition rate dividing means and square waveform generating means during the time the sampling pulse train is synchronized with the average time of occurrence of the zero slope points of the received analog data waveform, said adaptive threshold circuit means preventing any pulse outputs passing from said counter to said digital phase-shift circuit unless two identical commands of overflow or underflow are successively generated.

Claim 13

The automatic baud synchronizer set forth in claim 11 wherein said adaptive threshold circuit comprises a first circuit comprising a first pair of interconnected NAND logic gates and a first flip-flop wherein the input to said first circuit is connected to the overflow output of said counter, and a second circuit comprising a second pair of interconnected NAND logic gates and a second flip-flop wherein the input to said second circuit is connected to the underflow output of said counter, said first and second flip-flops having respective set direct input terminal connections to the underflow and overflow counter outputs whereby said adaptive threshold circuit passes an add or inhibit pulse to said digital phase-shift circuit only after two overflow or underflow pulses are successively developed at the output of said counter.

Claim 14

The automatic baud synchronizer set forth in claim 11 wherein said clock generator generates clock pulses at a repetition rate equal to 2n times the transmitted data rate, said sampling pulse train synchronizing means further comprises a divide-by-2 logic circuit having an input connected to the output of said clock generator and a first output supplying clock pulses at a repetition rate equal to 2n-1 times the transmitted data rate to a first of said sEcond inputs of said digital phase-shift circuit, a second of said second inputs of said digital phase-shift circuit supplied with the clock pulses at the 2n times repetition rate, the clock pulses supplied to said NAND logic gate circuit being of 2n times repetition rate, and the add and inhibit pulses generated in said digital phase-shift circuit each having a period equal to the period of a clock pulse at the 2n-1 times repetition rate, said clock generator pulse output repetition rate dividing means comprising divide-by-2n-1 logic circuitry to thereby obtain the sampling pulse train repetition rate equal to the transmitted data rate in said converter.

Claim 15

The automatic baud synchronizer set forth in claim 11 wherein said clock generator generates clock pulses at a repetition rate equal to 2n times the transmitted data rate, said sampling pulse train synchronizing means further comprises a divide-by-2 logic circuit having an input connected to the output of said clock generator and a first output supplying clock pulses at a repetition rate equal to 2n-1 times the transmitted data rate to a first of said second inputs of said digital phase shift circuit, a second of said second inputs of said digital phase-shift circuit supplied with the clock pulses at the 2n times repetition rate, the clock pulses supplied to said NAND logic gate circuit being of 2n times repetition rate, and the add and inhibit pulses generated in said digital phase-shift circuit each having a period equal to the period of a clock pulse at the 2n-1 times repetition rate, said clock generator pulse output repetition rate dividing means comprising divide-by-4 logic circuitry to thereby obtain the sampling pulse train at a repetition rate equal to 2n-3 times the transmitted data rate, and said analog-to-digital converter further comprising divide-by 2n-3 logic circuitry to thereby obtain the sampling pulse train repetition rate equal to the transmitted data rate.