Scaling and number base converting method and apparatus

Claim 2

Data processing means for converting a binary coded integer signal to a binary coded fraction signal in a predetermined number base the combination comprising: means for receiving such binary coded integer signal to be converted, counting means for counting through a sequence of states at least equal in number to the minimum number of significant digit signals, in such number base, desired in the fraction signal, means responsive to each state of said counting means for providing a series of binary coded digit signals, the series of binary coded digit signals thus provided representing a fractional numBer needed for converting the integer signal to a fraction signal, and means for combining the series of binary coded digit signals and the received integer signal for producing a product thereof representing such binary coded fraction signal.

Claim 3

Data processing means according to claim 1 wherein said combining means comprises: means for providing a binary coded output signal representative of the product of each digit signal and the integer signal, register means, adder means for combining the content of said register means with the product signals as they are formed to provide binary coded partial product signals, the register means being coupled for storing the first product signals formed and said partial product signals as they are formed; and means for controlling said counting means and register means causing the product and partial product signals stored in said register means to be shifted by one of said digit signals before combining and causing the counting means to count.

Claim 4

Data processing means according to claim 1 including register means coupled to the combining means for storing the received binary coded integer signal to be converted.

Claim 5

Data processing means according to claim 3 including further register means coupled to said combining means, said further register means storing a further binary coded integer signal forming the most significant portion of an extension of said integer signals, register means for temporarily storing the binary coded fraction signals converted from the first mentioned integer signal, means for setting the counting means and for causing the same to count through a sequence of states at least equal in number to the minimum number of significant digit signals in such number base desired in the fraction signals for both the first integer signal and the further integer signal, said means for providing a series of binary coded digit signals being operative for providing a binary coded digit signal for each of said states of said counting means, and means for combining the binary coded fraction signals from the first mentioned integer signals with the binary coded fraction signals formed from the further integer signals to form the resulting binary coded fraction signal.

Claim 6

Data processing means according to claim 1 wherein said combining means comprises means for providing a binary coded output signal representative of the product of each binary coded digit signal and the binary coded integer signal, accumulator register means, adder means for combining the signals from said combining means and the content of said accumulator register means and for storing the resultant signals in said accumulator register means, means for controlling said accumulator register means causing a digit shift therein for each said state of said counting means, gating means for said register means back to said adder means for each said state of said counting means thereby causing a true partial product to be formed by the adder means until the last of said binary coded output signals is combined and the final resulting fraction signal is formed by the adder means.

Claim 7

Data processing means according to claim 5 comprising register means for storing the digit signals shifted out of said accumulator register means from such digit shifts and thereby allow integer signals of extended length to be converted.

Claim 8

Data processing means according to claim 1 wherein the means for providing binary coded output signals comprises a decoder.

Claim 11

A method according to claim 8 wherein said series of states of the counter include at least as many states as there are significant digits desired in the fractional signal.

Claim 12

A method according to claim 8 wherein said step of combining includes the steps of multiplying each of said binary coded digit signals times the binary integer signal and for producing a product signal for each said binary coded digit signals forming a sum signal following each said product signals, shifting each said product signal and sum signal relative to each other one of such digit signals, the step of forming said sum signal including the step of combining said shifted signals to form output signals corresponding to the sum thereof.

Claim 13

A method according to claim 9 wherein the binary coded integer signal may include a further binary coded integer signal forming the most significant portion of such integer signal, including the steps of repeating the preceding steps using the further integer signals as the integer signal to be converted, the step of setting the counter including the step of setting the counter to a state corresponding to the total number of significant digit signals in such number base desired in the fractional signals for both the integer and further integer signals, and the series of states of such counter including at least as many states as there are significant digits desired in the fractional signals for both such integer and further integer signals, thereby causing a second but intermediate binary coded fractional signal to be formed and including the further step of combining the binary coded fractional signal obtained from the conversion of said integer signal with the second binary coded fractional signal obtained from conversion of said further integer signal to produce the final binary coded fractional signal.

Claim 16

Arithmetic apparatus for converting binary signals coded in a first number base to binary signals coded in a second number base, the combination comprising a full binary adder having a carry input circuit to the least significant position and two further inputs and an output, each of the adder means further inputs and the output comprising a plurality of circuits each circuit having a different binary weighted significance, first gating means coupling signals from said circuits of said adder means output to said circuits of both said adder means further inputs, the circuits of at least one input being of different binary weight than the circuits of said output from which the signals are couPled leaving a plurality of said circuits of at least one of said further inputs uncoupled, means for providing a plurality of binary coded digit signals for conversion, each digit signal comprised of binary bits, and second gating means for serially coupling the binary bits of said digit signals to said uncoupled circuits and to said carry input circuit.

Claim 17

Arithmetic apparatus for converting binary signals coded in a first number base to binary signals coded in a second number base, the combination comprising a full binary adder having a carry input circuit to the least significant position and two further inputs and an output, each of the adder means further inputs and the output comprising a plurality of circuits each circuit having a different binary weighted significance, first gating means coupling signals from said circuits of said adder means output to said circuits of both said adder means further inputs, the circuits of at least one input being of different binary weight than the circuits of said output from which the signals are couPled leaving a plurality of said circuits of at least one of said further inputs uncoupled, means for providing a plurality of binary coded digit signals for conversion, each digit signal comprised of binary bits, and second gating means for serially coupling the binary bits of said digit signals to said uncoupled circuits and to said carry input circuit.

Claim 18

Arithmetic apparatus according to claim 13 comprising means for activating said first and second gating means causing signals from said providing means and signals from circuits in said adding means output to be coupled to the circuits in said adder means input substantially simultaneously.

Claim 19

Arithmetic apparatus according to claim 13 wherein said means for providing binary coded digit signals comprises storage means.

Claim 20

Arithmetic apparatus according to claim 15 comprising third gating means for coupling signals from preselected circuits in said adder means output to said storage means.

Claim 21

Arithmetic apparatus according to claim 16 comprising register means coupled in between said output of said adder means and said first gating means for storing signals to be converted, means for activating said first gating means a plurality of times thereby causing the content of said register means to be applied to said adder means input a plurality of times and each time the resultant signals formed by said adder means being stored in said register means, said means for activating being operative for activating said third gating means a plurality of times causing signals from said preselected circuits in said adder output to be stored in said storage means.

Claim 22

Data processing apparatus for converting a series of binary coded decimal digit signals to binary signals coded in octal, each decimal digit having four binary bits respectively weighted 1- 2- 4- 8, the apparatus comprising, a full parallel binary adder having two inputs, a least significant position carry input and an output, each said input comprising 0, least significant, through m, most significant, binary weighted input circuits and the output comprising 0, least significant, through n, most significant, binary weighted output circuits, means for coupling said 0 through n output circuits to input circuits 3 through 3 +n of a first one of said inputs and to input circuits 1 through 1 +n of the second one of said inputs, and means for applying said binary coded decimal digit signals, a digit at a time, to said adder comprising means for applying binary bit 8 to said carry input and to input circuits 0, 1 and 2 of said first input and to input circuit 0 of said second input and means for applying bits 1, 2 and 4 to input circuits 0, 1 and 2 of said second input thereby causing the adder to form output signals corresponding to the product of ten times the output signals from said adding means plus the digit signal being applied.

Claim 23

Data processing apparatus for converting a series of binary coded decimal digit signals to binary signals coded in octal, each decimal digit having four binary bits respectively weighted 1- 2- 4- 8, the apparatus comprising, a full parallel binary adder having two inputs, a least significant position carry input and an output, each said input comprising 0, least significant, through m, most significant, binary weighted input circuits and the output comprising 0, least significant, through n, most significant, binary weighted output circuits, means for coupling said 0 through n output circuits to input circuits 3 through 3 +n of a first one of said inputs and to input circuits 1 through 1 +n of the second one of said inputs, and means for applying said binary coded decimal digit signals, a digit at a time, to said adder comprising means for applying binary bit 8 to said carry input and to input circuits 0, 1 and 2 of said first input and to input circuit 0 of said second input and means for applying bits 1, 2 and 4 to input circuits 0, 1 and 2 of said second input thereby causing the adder to form output signals corresponding to the product of ten times the output signals from said adding means plus the digit signal being applied.

Claim 28

Apparatus for converting a binary coded octal integer signal into a most significant portion coded in binary coded octal and a least significant portion composed of binary coded decimal digits, the number of decimal digits being indicated by a scale factor signal, comprising means for counting a counter through a predetermined series of states; means for responding to each of said states for producing a series of octal coded digit signals representative of octal 12 n where n is at least as large as the maximum number of decimal digits desired in the result, means for combining the integer signal and each coded digit signal produced and for generating a fractional signal representative of the product of said series of coded digit signals and said integer signals, means for applying the fractional signal, and a series of product signals derived therefrom, to a multiplying means multiplying each by ten to produce product signals, the fraction signal and a total of at least n-1 product signals derived therefrom being applied to such multiplying means; means for storing the most significant signals, which represent a decimal digit, from each of said product signals, in the order formed, most significant to least significant; a two-input parallel adder which performs binary addition in octal coded form; means for serially applying the stored decimal digit signals, most significant to least significant, to an input of said adder, the number of decimal digit signals applied by said serial applying means being at least n minus the value of the scale factor signal; means for applying the adder output signals back to both inputs of such adder, shifted in binary significance with respect to at least one such input, such that the effective sum formed by the adder is the product of ten times the applied adder output signals plus the applied digit signal causing corresponding adder output signals, said means for applying adder output signals being operative for applying one such digit signal at a time simultaneously with the applying of each different one of said adder output signals, said adder output signals after all such digit signals are applied representing the most significant octal portion of the converted signal and the remaining stored decimal digit signals representing the least significant portion of the converted signal.

Claim 29

Apparatus for converting a binary coded octal integer signal into a most significant portion coded in binary coded octal and a least significant portion composed of binary coded decimal digits, the number of decimal digits being indicated by a scale factor signal, comprising means for counting a counter through a predetermined series of states; means for responding to each of said states for producing a series of octal coded digit signals representative of octal 12 n where n is at least as large as the maximum number of decimal digits desired in the result, means for combining the integer signal and each coded digit signal produced and for generating a fractional signal representative of the product of said series of coded digit signals and said integer signals, means for applying the fractional signal, and a series of product signals derived therefrom, to a multiplying means multiplying each by ten to produce product signals, the fraction signal and a total of at least n-1 product signals derived therefrom being applied to such multiplying means; means for storing the most significant signals, which represent a decimal digit, from each of said product signals, in the order formed, most significant to least significant; a two-input parallel adder which performs binary addition in octal coded form; means for serially applying the stored decimal digit signals, most significant to least significant, to an input of said adder, the number of decimal digit signals applied by said serial applying means being at least n minus the value of the scale factor signal; means for applying the adder output signals back to both inputs of such adder, shifted in binary significance with respect to at least one such input, such that the effective sum formed by the adder is the product of ten times the applied adder output signals plus the applied digit signal causing corresponding adder output signals, said means for applying adder output signals being operative for applying one such digit signal at a time simultaneously with the applying of each different one of said adder output signals, said adder output signals after all such digit signals are applied representing the most significant octal portion of the converted signal and the remaining stored decimal digit signals representing the least significant portion of the converted signal.

Claim 30

Data processing apparatus for shifting left a binary coded signal coded in a first number base by digits coded in a second base comprising: first register means for storing an operator identifying a left shift; second register means for storing a scale factor signal identifying the number of required left digit shifts; counter means; means responsive to said stored shift operator for counting said counter means through a sequence of states corresponding to said scale factor; at least a two-input parallel adder means operating in said first number base; means operative for each of said states of said counter means for applying the adder means output signal back to both inputs of said adder means, shifted in binary significance with respect to at least one such input, such that the resulting output signal formed by the adder means is the product of the second number base times the applied adder means output signals; and includes a binary coded decimal overflow digit signal; means responsive to said stored shift operator for selectively and initially applying a binary coded signal which is to be shifted, to said adder means causing an initial adder means output signal; third register means; means for storing each of said overflow digit signals into said third register means; said counting means being operative for causing said counter to recount through a subsequent sequence of states corresponding to said scale factor; means responsive to said stored shift operator for selectively applying said digit signals stored in said third register means, a digit at a time with each said subsequent states of said counting means, to an input of said adder means substantially simultaneously with said application of one of said adder means output signals thereby causing addition thereof into the sum being formed.

Claim 31

Data processing apparatus for shifting left a binary coded signal coded in a first number base by digits coded in a second base comprising: first register means for storing an operator identifying a left shift; second register means for storing a scale factor signal identifying the number of required left digit shifts; counter means; means responsive to said stored shift operator for counting said counter means through a sequence of states corresponding to said scale factor; at least a two-input parallel adder means operating in said first number base; means operative for each of said states of said counter means for applying the adder means output signal back to both inputs of said adder means, shifted in binary significance with respect to at least one such input, such that the resulting output signal formed by the adder means is the product of the second number base times the applied adder means output signals; and includes a binary coded decimal overflow digit signal; means responsive to said stored shift operator for selectively and initially applying a binary coded signal which is to be shifted, to said adder means causing an initial adder means output signal; third register means; means for storing each of said overflow digit signals into said third register means; said counting means being operative for causing said counter to recount through a subsequent sequence of states corresponding to said scale factor; means responsive to said stored shift operator for selectively applying said digit signals stored in said third register means, a digit at a time with each said subsequent states of said counting means, to an input of said adder means substantially simultaneously with said application of one of said adder means output signals thereby causing addition thereof into the sum being formed.

Claim 32

Data processing apparatus according to claim 22 wherein said first number base is octal.

Claim 33

Data processing apparatus according to claim 23 wherein said second number base is decimal.

Claim 34

Data processing apparatus according to claim 23 comprising control means for first activating said means for applying a binary coded signal to be converted and subsequently activating said means for selectively applying digit signals stored in said third register means.

Claim 35

Data processing apparatus for shifting a binary coded signal by digits coded in a predetermined number base comprising: first register means for storing an operator identifying a shift; second register means for storing a scale factor signal identifying the number of required digit shifts; counter means; means for selectively counting said counter means through a sequence of states including a sequence of states predetermined by said stored scale factor; two input parallel adder means; means operative for each of said states of said counter means for applying the adder means output signal back to both inputs of said adder means, shifted in binary significance with respect to at Least one such input, such that the resulting output signal formed by the adder means is the product of the predetermined number base times the applied adder means output signals and includes a binary coded overflow digit signal; means responsive to said stored shift operator for selectively applying a binary coded signal which is to be shifted, to said adder means causing an adder means output signal including a binary coded overflow digit signal; third register means; means for storing in said third register means each of said overflow digit signals; and means responsive to said stored shift operator for selectively applying digit signals stored in said third register means, a digit at a time with each said states of said counting means to an input of said adder means substantially simultaneously with the application of one of said adder means output signals thereby causing addition thereof into the sum being formed, said last mentioned applying means being operative for applying during the states of said counter which is predetermined by said scale factor.

Claim 36

Data processing apparatus for shifting a binary coded signal by digits coded in a predetermined number base comprising: first register means for storing an operator identifying a shift; second register means for storing a scale factor signal identifying the number of required digit shifts; counter means; means for selectively counting said counter means through a sequence of states including a sequence of states predetermined by said stored scale factor; two input parallel adder means; means operative for each of said states of said counter means for applying the adder means output signal back to both inputs of said adder means, shifted in binary significance with respect to at Least one such input, such that the resulting output signal formed by the adder means is the product of the predetermined number base times the applied adder means output signals and includes a binary coded overflow digit signal; means responsive to said stored shift operator for selectively applying a binary coded signal which is to be shifted, to said adder means causing an adder means output signal including a binary coded overflow digit signal; third register means; means for storing in said third register means each of said overflow digit signals; and means responsive to said stored shift operator for selectively applying digit signals stored in said third register means, a digit at a time with each said states of said counting means to an input of said adder means substantially simultaneously with the application of one of said adder means output signals thereby causing addition thereof into the sum being formed, said last mentioned applying means being operative for applying during the states of said counter which is predetermined by said scale factor.

Claim 37

Data processing apparatus according to claim 26 wherein said shift operator comprises a shift right operator wherein said counter states are equal to or less than the total number of digits in said third register means and thereby cause a signal to be formed which is partially in said predetermined number base and partially in the number base of said binary coded signal to be shifted.

Claim 38

Data processing apparatus for shifting a binary signal coded in a first number base by digits coded in a second number base comprising: register means for storing an operator identifying a shift; second register means for storing a scale factor signal identifying the number of required digit shifts; means for receiving a binary signal coded in said first number base; and means responsive to said stored shift operator signal and said stored scale factor signal for shifting said received binary signal, in said first number base, by the number of digits in said second number base which is identified by said stored scale factor.

Claim 39

Data processing apparatus for shifting a binary signal coded in a first number base by digits coded in a second number base comprising: register means for storing an operator identifying a shift; second register means for storing a scale factor signal identifying the number of required digit shifts; means for receiving a binary signal coded in said first number base; and means responsive to said stored shift operator signal and said stored scale factor signal for shifting said received binary signal, in said first number base, by the number of digits in said second number base which is identified by said stored scale factor.

Claim 40

Data processing apparatus according to claim 28 wherein said shift means is operative for effecting a right shift and comprises means responsive to said shift operator and said stored scale factor for converting the binary signal in said first number base to a signal having a fractional part comprising digits coded in said second number base, the number of such digits being identified by said scale factor, and an integer portion coded in said first number base.

Claim 41

Data processing apparatus according to claim 28 wherein said shift means is operative for effectively shifting left and comprises means for shifting left said received binary signal coded in said first number base by multiplying same times said second number base.

Claim 42

Data processing apparatus according to claim 28 wherein said operators may specify a shift left or a shift right and wherein said shift means comprises means responsive to a stored shift right operator for shifting said received binary signal to the right, in said first number base, by the number of digits of said second number base specified by said scale factor and means responsive to a stored shift left operator for shifting said received binary signal to the left, in said first number base, by the number of digits of said second number base specified by said stored scale factor.

Claim 43

Data processing apparatus according to claim 9 wherein said means responsive to a shift left operator comprises means for converting said received binary signal to a fractional signal, means for converting said fractional signals to binary signals coded in said second number base which fractional signal comprises ''''Y'''' binary digits, and means for converting ''''Y'''' minus said scale factor of the digits in said fractional signal back to a binary signal coded in said first number base.

Claim 44

Data processing apparatus for shifting a binary signal coded in A first number base by digits coded in a second number base comprising: register means for storing an operator identifying a shift; register means for storing a scale factor signal identifying the number of required digit shifts; means for receiving a binary signal coded in said first number base; means responsive to said stored scale factor operator for shifting said received binary signals in said first number base by digits in said second number base and comprising means at least partially converting said received binary signals to at least one intermediate binary digit signal coded in said second number base; means for converting the number of the digits in said intermediate signal back to said first number base wherein the number of digits is specified by a control signal; and means responsive to said stored scale factor for applying said control signal to said conversion means identifying the number of digits to be converted.

Claim 45

Data processing apparatus for shifting a binary signal coded in A first number base by digits coded in a second number base comprising: register means for storing an operator identifying a shift; register means for storing a scale factor signal identifying the number of required digit shifts; means for receiving a binary signal coded in said first number base; means responsive to said stored scale factor operator for shifting said received binary signals in said first number base by digits in said second number base and comprising means at least partially converting said received binary signals to at least one intermediate binary digit signal coded in said second number base; means for converting the number of the digits in said intermediate signal back to said first number base wherein the number of digits is specified by a control signal; and means responsive to said stored scale factor for applying said control signal to said conversion means identifying the number of digits to be converted.

Claim 46

Data processing apparatus according to claim 51 wherein said intermediate signal comprises ''''Y'''' digits, wherein said shift operator identifies a right shift and the control signal applying means applies a signal corresponding to ''''Y'''' minus the scale factor of digits to be converted, said conversion means being operative for converting the number of most significant digits specified by said control signal.

Claim 47

Data processing apparatus according to claim 33 wherein said shift operator identifies a left shift and the control signal applying means applies a control signal corresponding to the scale factor, said conversion means being operative for converting the number of most significant digits specified by said control signals.