Signal-converting method and apparatus

Claim 3

A device as defined in claim 1 wherein said first and third signals are substantially linear ramp signals.

Claim 4

A device as defined in claim 1 wherein said means for measuring said time period is adapted to provide the latter as a digital count.

Claim 5

A device as defined in claim 1 wherein said third signal has an initial absolute value which is a predetermined multiple of the absolute amplitude value of said second signal at the end of said predetermined cycle.

Claim 6

A device as defined in claim 1 wherein said second signal has an initial absolute amplitude value which is substantially the same as the absolute value of amplitude of said first signal at the time of coincidence between said first signal and said input signal.

Claim 7

A device as defined in claim 5 wherein said third signal has an initial value which is substantially the same as the absolute amplitude value of said second signal at the end of said predetermined cycle.

Claim 8

A device as defined in claim 1 wherein said reference level has substantially the same amplitude value as the absolute amplitude value of said first signal at the time of coincidence between said first signal and said input signal.

Claim 9

A device as defined in claim 1 including means for generating an output signal proportional to said time period.

Claim 10

An analog-to-digital antilog converter for converting an input analog logarithmic signal to a digital antilog output signal, said converter comprising: a clock circuit for providing a clocking signal having a predetermined cycle; a first linear ramp generator connected to said clock circuit for generating a first ramp signal beginning at the start of said cycle; a first comparator circuit to which said input signal and ramp signal are applied for determining coincidence between said input signal and ramp signal; means coupled to the output of said first comparator circuit for generating a signal which varies exponentially with time when coincidence occurs between said ramp signal and input signal, said exponential signal having an asymptotic charging amplitude and time constant of predetermined value; a second linear ramp generator coupled to the output of said clock circuit for providing a second ramp signal having absolute value of slope determined in accordance with the instantaneous absolute value of slope of said first ramp signal and beginning at the end of said predetermined cycle, said second ramp signal having an initial absolute amplitude value in accordance with the absolute amplitude value of said exponential signal at the end of said cycle; a second comparator circuit coupled to the output of said second ramp generator for determining coincidence between said second ramp signal and a reference signal having an amplitude value determined in aCcordance with the value of said input signal; and means for counting, in accordance with said clock, the time period from the end of said predetermined cycle to the time when a predetermined coincidence occurs between said second ramp signal and said reference signal, said time period being proportional to the antilog of said input signal.

Claim 11

An analog-to-digital antilog converter for converting an input analog logarithmic signal to a digital antilog output signal, said converter comprising: a clock circuit for providing a clocking signal having a predetermined cycle; a first linear ramp generator connected to said clock circuit for generating a first ramp signal beginning at the start of said cycle; a first comparator circuit to which said input signal and ramp signal are applied for determining coincidence between said input signal and ramp signal; means coupled to the output of said first comparator circuit for generating a signal which varies exponentially with time when coincidence occurs between said ramp signal and input signal, said exponential signal having an asymptotic charging amplitude and time constant of predetermined value; a second linear ramp generator coupled to the output of said clock circuit for providing a second ramp signal having absolute value of slope determined in accordance with the instantaneous absolute value of slope of said first ramp signal and beginning at the end of said predetermined cycle, said second ramp signal having an initial absolute amplitude value in accordance with the absolute amplitude value of said exponential signal at the end of said cycle; a second comparator circuit coupled to the output of said second ramp generator for determining coincidence between said second ramp signal and a reference signal having an amplitude value determined in aCcordance with the value of said input signal; and means for counting, in accordance with said clock, the time period from the end of said predetermined cycle to the time when a predetermined coincidence occurs between said second ramp signal and said reference signal, said time period being proportional to the antilog of said input signal.

Claim 12

A converter as defined in claim 9 wherein: said exponential signal generating means includes a source of potential; charging means for generating said exponential signal; a first normally open switching means for connecting the output of source of potential to the input of said charging means, said switching means being closed by the signal from said first comparator circuit when coincidence occurs between said input signal and said first ramp signal to initiate operation of said charging means; and a second normally open switching means coupled to the output of said charging means and said counting means, said first switching means being opened and said second switching means being closed when said counting means is automatically reset at the end of said predetermined cycle to initiate operation of said second ramp generator.

Claim 13

A converter as defined in claim 9 wherein said second ramp signal has an instantaneous value of slope substantially the same as that of said first ramp signal and an initial value which is substantially the same as the absolute amplitude value of said exponential signal at the end of said predetermined cycle, and wherein said reference signal has substantially the same amplitude value as the initial amplitude value of said exponential signal.