Program-controlled data-processing system

Claim 2

A program-controlled data-processor system comprising a control arrangement for executing sequences of program order words, a memory system containing sequences of program order words and data and an input-output system; said control arrangement comprises first and second circuit arrangements, each comprising a register circuit and a decoding circuit, said first circuit arrangement is responsive to the instruction portion of a first order word of a sequence and generates control signals to control a portion of said control arrangement, said second circuit arrangement is responsive to a second order word of said sequence and generates further control signals in accordance with said instruction portion of said second order word, a third circuit arrangement which generates and transmits a coded signal to said memory system to obtain for said second circuit arrangement a third order word of said sequence, and said control arrangement transfers each succeeding order word from said second circuit arrangement to said first circuit arrangement at a particular time in each control arrangement time cycle, said third, second and first circuit arrangements being individually operative with respect to each order word which is executed by said control arrangement and said third, said second and said first circuit arrangements are contemporaneously operative with respect to three successive order words.

Claim 3

In combination, memory means; and a central control comprising: memory-accessing means for generating and transmitting commands for reading information from said memory means, clock means defining central control machine cycles, a buffer order word register connected to buffer order word decoding means for controlling portions of said central control in response to instructions in said buffer order word register, an order word register connected to order word decoding means for controlling portions in said central control in response to instructions in said order word register, means including said clock means for transferring the contents of a portion of said buffer order word register to said order word register at a distinct time in said central control machine cycle, and circuit means for controlling said memory-accessing means for transferring an immediately succeeding order word into said buffer order register at a second distinct later time, the difference in time between said first and second said distinct times being less than the time required to obtain information from said memory arrangement, said buffer order decoding means and said order word decoding means; said buffer order word decoding means, said order word decoding means and said memory accessing means being individually operative with respect to each order word which is executed by said control arrangement and operative on an overlap basis with respect to three successive instructions.

Claim 4

In combination, memory means; and a central control comprising: memory-accessing means for generating and transmitting commands for reading information from said memory means, clock means defining central control machine cycles, a buffer order word register connected to buffer order word decoding means for controlling portions of said central control in response to instructions in said buffer order word register, an order word register connected to order word decoding means for controlling portions in said central control in response to instructions in said order word register, means including said clock means for transferring the contents of a portion of said buffer order word register to said order word register at a distinct time in said central control machine cycle, and circuit means for controlling said memory-accessing means for transferring an immediately succeeding order word into said buffer order register at a second distinct later time, the difference in time between said first and second said distinct times being less than the time required to obtain information from said memory arrangement, said buffer order decoding means and said order word decoding means; said buffer order word decoding means, said order word decoding means and said memory accessing means being individually operative with respect to each order word which is executed by said control arrangement and operative on an overlap basis with respect to three successive instructions.

Claim 5

The combination in accordance with claim 2 wherein said memory means comprises a program store for storing sequences of instructions and data and a call store for storing data, and said central control compRises means for simultaneously communicating with said program store and said call store.

Claim 6

In combination, a program store containing sequences of program order words and data, a data store containing data, a central control comprising means for reading information from said stores, a buffer order word register, a buffer order word decoder responsive to information stored in said buffer order word register for controlling said central control, an order word register, an order word decoder responsive to said information stored in said order word register for controlling said central control, and said central control includes means for simultaneously communicating with said program store and with said data store.

Claim 7

In combination, a program store containing sequences of program order words and data, a data store containing data, a central control comprising means for reading information from said stores, a buffer order word register, a buffer order word decoder responsive to information stored in said buffer order word register for controlling said central control, an order word register, an order word decoder responsive to said information stored in said order word register for controlling said central control, and said central control includes means for simultaneously communicating with said program store and with said data store.

Claim 8

In combination, a plurality of control circuits, a central control, a first memory means for storing sequences of program order words and first data, a second memory means for storing other data, and transmission means interconnecting said central control with said first memory means, said second memory means and said control circuits; said central control comprising means responsive to said program order words for concurrently: a. carrying out data processing in response to a first order word, b. carrying out data processing in response to an immediately succeeding second order word, and c. generating and transmitting a coded signal to said first memory means to obtain a third order word therefrom.

Claim 9

In combination, a plurality of control circuits, a central control, a first memory means for storing sequences of program order words and first data, a second memory means for storing other data, and transmission means interconnecting said central control with said first memory means, said second memory means and said control circuits; said central control comprising means responsive to said program order words for concurrently: a. carrying out data processing in response to a first order word, b. carrying out data processing in response to an immediately succeeding second order word, and c. generating and transmitting a coded signal to said first memory means to obtain a third order word therefrom.

Claim 10

The combination in accordance with claim 5 wherein said data processing in response to said second order word includes the generation and transmission of a code-address to said second memory means to obtain a data reading therefrom. 7. A program-controlled data-processor system in accordance with claim 2 wherein said control arrangement further comprises: a mixed decoder responsive to instructions simultaneously stored in said order word register and in said buffer order word register for altering the responses of said buffer order word decoding means.

Claim 11

A program-controlled data-processor system in accordance with claim 7 wherein said control arrangement further comprises a plurality of flip-flop registers, and a masked bus connected to input terminals of said flip-flop registers, an unmasked bus connected to output terminals of said flip-flop registers, and wherein when the order word currently in said order word register is a data reading order which specifies a particular flip-flop register within central control as the destination for the data read and the order word currently in the buffer order word register specifies said destination register as a source register for indexing, said mixed decoder in response to said specified order words alters the operation of said buffer order word decoding means to substitute the information occurring on said masked bus for information occurring on said unmasked bus for indexing.

Claim 12

In combination, a memory arrangement, a central control comprising means for reading information from said memory arrangement, a buffer order word register, an order word register, a buffer order word decoder responsive to information stored in a portion of said buffer order word register for controlling said central control, an order word decoder responsive to the information stored in said order word register for controlling said central control, means for transferring information from said buffer order word register to said order word register in distinct times defined by a clock circuit in said central control, said buffer order word decoder and said order word decoder being operative with respect to each successive order word and a mixed decoder connected to said buffer order word register and to said order word register and responsive to information stored in said order word register and a portion of said information stored in said buffer order word register for altering the responses of said buFfer order word decoder.

Claim 13

In combination, a memory arrangement, a central control comprising means for reading information from said memory arrangement, a buffer order word register, an order word register, a buffer order word decoder responsive to information stored in a portion of said buffer order word register for controlling said central control, an order word decoder responsive to the information stored in said order word register for controlling said central control, means for transferring information from said buffer order word register to said order word register in distinct times defined by a clock circuit in said central control, said buffer order word decoder and said order word decoder being operative with respect to each successive order word and a mixed decoder connected to said buffer order word register and to said order word register and responsive to information stored in said order word register and a portion of said information stored in said buffer order word register for altering the responses of said buFfer order word decoder.

Claim 14

In combination, a program store, means for reading information from said program store, and means responsive to said information read from said store, said means responsive including a system clock defining discrete machine cycles, phases within said cycles, and periods of time within each of said phases, said program order words comprising a data address field, an operation field, and a check field, said central control comprising a buffer order word register arranged to receive all of said elements of said program order word, an auxiliary buffer order word register interposed between said program store and the operation portion of said buffer order word register, and gating means interposed between the output terminals of said auxiliary buffer order word register and the operation portion of said buffer order word register, and control means responsive to said clock means for gating the contents of said auxiliary buffer order word register to said buffer order word register.

Claim 15

In combination, a program store, means for reading information from said program store, and means responsive to said information read from said store, said means responsive including a system clock defining discrete machine cycles, phases within said cycles, and periods of time within each of said phases, said program order words comprising a data address field, an operation field, and a check field, said central control comprising a buffer order word register arranged to receive all of said elements of said program order word, an auxiliary buffer order word register interposed between said program store and the operation portion of said buffer order word register, and gating means interposed between the output terminals of said auxiliary buffer order word register and the operation portion of said buffer order word register, and control means responsive to said clock means for gating the contents of said auxiliary buffer order word register to said buffer order word register.

Claim 16

In combination, a program store containing sequences of program order words, certain of said order words being data-processing-transfer order words, a data store containing system data, a central control comprising means for obtaining information from said stores, for writing information into said data store and for executing said sequences of program order words, means responsive to the execution of said data processing-transfer order words for generating transfer signals and advance signals, and means responsive to said advance signals for carrying out data processing specified by a portion of said data processing-transfer order words.

Claim 17

In combination, a program store containing sequences of program order words, certain of said order words being data-processing-transfer order words, a data store containing system data, a central control comprising means for obtaining information from said stores, for writing information into said data store and for executing said sequences of program order words, means responsive to the execution of said data processing-transfer order words for generating transfer signals and advance signals, and means responsive to said advance signals for carrying out data processing specified by a portion of said data processing-transfer order words.

Claim 18

In combination, a memory system containing sequences of program order words and data, said sequences including data processing-decision order words; a central control comprising means for reading information from said memory system and for writing data into said memory system, means for executing said program sequences, a plurality of flip-flop registers, a plurality of data processing means, means responsive to said data processing-decision order words to examine the contents of a selected one of said flip-flop registers, and means responsive to the states of said selected flip-flop register and said data processing-decision order words for generating control signals for said data processing means.

Claim 19

In combination, a memory system containing sequences of program order words and data, said sequences including data processing-decision order words; a central control comprising means for reading information from said memory system and for writing data into said memory system, means for executing said program sequences, a plurality of flip-flop registers, a plurality of data processing means, means responsive to said data processing-decision order words to examine the contents of a selected one of said flip-flop registers, and means responsive to the states of said selected flip-flop register and said data processing-decision order words for generating control signals for said data processing means.

Claim 20

A program controlled data processor system comprising a data bus system including an unmasked bus, a mask and complement circuit, and a masked bus, a plurality of flip-flop registers connected to said bus system, and a homogeneity circuit connected to said bus system for observing the homogeneity of data words transmitted over said bus system, a control homogeneity flip-flop responsive to output signals of said homogeneity circuit for generating signals representing the homogeneity of observed data words, a control sign circuit for observing a specified sign bit of data words transmitted via said bus system, a control sign flip-flop responsive to output signals of said control sign circuit for generating output signals representative of the sign of observed data words, memory means containing sequences of program order words and data, program order word register means, means for transferring program order words from said memory means to said program order word register means, decoding means responsive to said program order words, and decision logic responsive to the output signals of said control homogeneity flip-flop and said control sign flip-flop and to output signals of said decoding means for generating system advance and system transfer signals for determining the next program order word to be obtained from said memory means.

Claim 21

A program controlled data processor system comprising a data bus system including an unmasked bus, a mask and complement circuit, and a masked bus, a plurality of flip-flop registers connected to said bus system, and a homogeneity circuit connected to said bus system for observing the homogeneity of data words transmitted over said bus system, a control homogeneity flip-flop responsive to output signals of said homogeneity circuit for generating signals representing the homogeneity of observed data words, a control sign circuit for observing a specified sign bit of data words transmitted via said bus system, a control sign flip-flop responsive to output signals of said control sign circuit for generating output signals representative of the sign of observed data words, memory means containing sequences of program order words and data, program order word register means, means for transferring program order words from said memory means to said program order word register means, decoding means responsive to said program order words, and decision logic responsive to the output signals of said control homogeneity flip-flop and said control sign flip-flop and to output signals of said decoding means for generating system advance and system transfer signals for determining the next program order word to be obtained from said memory means.

Claim 22

A program-controlled system comprising means for obtaining program order words, means for obtaininG data, a plurality of homogeneity circuits for observing the homogeneity of data occurring in various portions of said system, a plurality of sign circuits for observing the sign of data words occurring at various locations within said system, decision logic connected to output terminals of said plurality of homogeneity circuits and said sign circuits, and decoding means responsive to said program order words for controlling said system, said decision logic responsive to output signals of said decoding means for generating program advance and program transfer signals in accordance with homogeneity and sign information occurring on selected ones of said homogeneity and said sign circuit output conductors, said selection being determined by output signals of said decoding means.

Claim 23

A program-controlled system comprising means for obtaining program order words, means for obtaininG data, a plurality of homogeneity circuits for observing the homogeneity of data occurring in various portions of said system, a plurality of sign circuits for observing the sign of data words occurring at various locations within said system, decision logic connected to output terminals of said plurality of homogeneity circuits and said sign circuits, and decoding means responsive to said program order words for controlling said system, said decision logic responsive to output signals of said decoding means for generating program advance and program transfer signals in accordance with homogeneity and sign information occurring on selected ones of said homogeneity and said sign circuit output conductors, said selection being determined by output signals of said decoding means.

Claim 24

In a program-controlled system, the combination in accordance with claim 14 wherein said decoding means comprises a buffer order word decoder and an order word decoder, said decision logic responsive to output signals of said buffer order word decoder and said homogeneity and said sign circuits to generate system advance and system early transfer signals, said decision logic responsive to output signals of said order word decoder and of said homogeneity circuits and said sign circuits to generate system advance and system late transfer signals.

Claim 25

A program-controlled data processor for controlling an input-output system comprising: a program store containing sequences of program order words, said program order words comprising nondecision orders and decision orders, said decision orders comprising a first class of orders which specify a data reading or writing after a decision to advance has been reached, a second class of orders which do not specify a data reading or writing after said decision to advance has been reached; a central control comprising clock means defining a discrete machine cycle, and a plurality of discrete times within said cycle, decision logic, and means for reading said sequences of program order words from said program store, and means responsive to said program order words for controlling said input-output system, said means responsive comprising a buffer order word register, a buffer order word decoder, said buffer order word decoder effective to generate control signals for said decision logic in response to orders of said first class for causing said decision logic to generate advance signals and early transfer signals at a first discrete time in said machine cycle, said central control further comprising an order word register, and an order word decoder, said order word decoder responsive to order words of said second class to generate control signals for said decision logic for causing said decision logic to generate system advance and system late transfer signals at a second discrete time in said machine cycle.

Claim 26

A program-controlled data processor for controlling an input-output system comprising: a program store containing sequences of program order words, said program order words comprising nondecision orders and decision orders, said decision orders comprising a first class of orders which specify a data reading or writing after a decision to advance has been reached, a second class of orders which do not specify a data reading or writing after said decision to advance has been reached; a central control comprising clock means defining a discrete machine cycle, and a plurality of discrete times within said cycle, decision logic, and means for reading said sequences of program order words from said program store, and means responsive to said program order words for controlling said input-output system, said means responsive comprising a buffer order word register, a buffer order word decoder, said buffer order word decoder effective to generate control signals for said decision logic in response to orders of said first class for causing said decision logic to generate advance signals and early transfer signals at a first discrete time in said machine cycle, said central control further comprising an order word register, and an order word decoder, said order word decoder responsive to order words of said second class to generate control signals for said decision logic for causing said decision logic to generate system advance and system late transfer signals at a second discrete time in said machine cycle.

Claim 27

In combination, a program order word information source; a data word information source; and a central control responsive to information read from said information sources for determining the operation thereof, said central control comprising a plurality of general purpose flip-flop registers, an accumulator register, an accumulator register input circuit, and an accumulator register homogeneity circuit for observing the homogeneity of the contents of said accumulator register.

Claim 28

In combination, a program order word information source; a data word information source; and a central control responsive to information read from said information sources for determining the operation thereof, said central control comprising a plurality of general purpose flip-flop registers, an accumulator register, an accumulator register input circuit, and an accumulator register homogeneity circuit for observing the homogeneity of the contents of said accumulator register.

Claim 29

The combination in accordance with claim 17 wherein central control further comprises an accumulator logic homogeneity circuit for observing the homogeneity of information appearing at the output terminals of said accumulator input circuit.

Claim 30

In a central control of a program-controlled system, an accumulator register circuit, first and second accumulator input registers, an accumulator register logic circuit for selectively logically combining the contents of said first and second accumulator input registers, gating means for transmittiNg output signals from said accumulator logic circuit to said accumulator register, and a rotate-shift circuit, the input terminals of said rotate-shift circuit connected to the output terminals of said accumulator register, the output terminals of said rotate-shift circuit connected to the input terminals of said accumulator register, a rotate-shift distance and direction information source connected to distance and direction terminals of said rotate-shift circuit, and means in said central control for selectively generating rotate-shift control signals, said rotate-shift circuit responsive to said input signals at said distance and direction terminals and to said control signals for generating at said output terminals thereof a data word resulting from the selective shifting and rotating of the data word occurring at the output terminal of said accumulator register.

Claim 31

In a central control of a program-controlled system, an accumulator register circuit, first and second accumulator input registers, an accumulator register logic circuit for selectively logically combining the contents of said first and second accumulator input registers, gating means for transmittiNg output signals from said accumulator logic circuit to said accumulator register, and a rotate-shift circuit, the input terminals of said rotate-shift circuit connected to the output terminals of said accumulator register, the output terminals of said rotate-shift circuit connected to the input terminals of said accumulator register, a rotate-shift distance and direction information source connected to distance and direction terminals of said rotate-shift circuit, and means in said central control for selectively generating rotate-shift control signals, said rotate-shift circuit responsive to said input signals at said distance and direction terminals and to said control signals for generating at said output terminals thereof a data word resulting from the selective shifting and rotating of the data word occurring at the output terminal of said accumulator register.

Claim 32

The system in accordance with claim 19 wherein said central control further comprises an indexing system, said indexing system comprising an addend register, an augend register, an index adder for adding the contents of said addend and said augend registers, an index adder output register, and wherein the output terminals of said index adder are connected to said distance and direction input terminals.

Claim 33

The system in accordance with claim 24 wherein said rotate-shift distance and direction information source provides an (n+1)-bit word, the first n bits of said word comprising a code word defining the distance said rotate-shift circuit is to rotate or shift the word occurring at the input terminals thereof and the remaining bit of said word defining the direction of rotation or shift.

Claim 34

The system in accordance with claim 19 wherein said rotate-shift control signals comprise: a. a rotate signal, b. a shift signal, c. a limited rotate signal, and d. a complement signal, said complement signal effective to reverse the direction of shift or rotate specified by said distance and direction information source.

Claim 35

In combination, a flip-flop register, a rotate-shift circuit, input terminals of said rotate-shift circuit connected to the output terminals of said flip-flop register, output terminals of said rotate-shift circuit connected to the input terminals of said rotate-shift circuit, an indexing system comprising an addend register, an augend register, an index adder for adding the contents of said addend and said augend registers, an index adder output register, the output terminals of said index adder connected to distance and direction input terminals of said rotate-shift circuit, means in said central control for generating rotate-shift control signals, said rotate-shift circuit responsive to said input signals at said distance and direction terminals and to said control signals for generating at said output terminals thereof a data word resulting from the selective shifting and rotating of the data word occurring at the output terminals of said flip-flop register.

Claim 36

In combination, a flip-flop register, a rotate-shift circuit, input terminals of said rotate-shift circuit connected to the output terminals of said flip-flop register, output terminals of said rotate-shift circuit connected to the input terminals of said rotate-shift circuit, an indexing system comprising an addend register, an augend register, an index adder for adding the contents of said addend and said augend registers, an index adder output register, the output terminals of said index adder connected to distance and direction input terminals of said rotate-shift circuit, means in said central control for generating rotate-shift control signals, said rotate-shift circuit responsive to said input signals at said distance and direction terminals and to said control signals for generating at said output terminals thereof a data word resulting from the selective shifting and rotating of the data word occurring at the output terminals of said flip-flop register.

Claim 37

In combination, an accumulator register and a detect first-one circuit connected to the output terminals of said accumulator register for generating coded data words defining the first bit position of said accumulator register in which a 1 occurs.

Claim 38

In combination, an accumulator register and a detect first-one circuit connected to the output terminals of said accumulator register for generating coded data words defining the first bit position of said accumulator register in which a 1 occurs.

Claim 39

The combination in accordance with claim 24 further comprising a first-one register, means for selectively connecting the output terminals of said first-one circuit to the input terminals of said first-one register, a reset first-one circuit for generating reset signals, the input terminals of said reset first-one circuit connected to the output terminals of said first-one register, and means for generating a reset first-one control signal, and a plurality of AND-gates, the output terminals of said reset first-one circuit connected to the reset input termiNals of said accumulator register via said plurality of AND-gates, and means for controlling said plurality of AND-gates by said reset first-one control signal.

Claim 40

The combination in accordance with claim 25 wherein said reset first-one circuit comprises a translator for converting an n-bit binary code to a 1-out-of N code.

Claim 41

In combination, a memory, sequences of program order words, and a central control, said central control comprising a masked bus, an unmasked bus, means for generating code-addresses for obtaining program order words from said memory, said means including a program address register, means for transmitting said code-addresses to said memory, and means for incrementing said code-addresses by a count of 1, said means for incrementing comprising an add-one register having input terminals connected to the output terminals of said program address register, an add-one circuit having input terminals connected to the output terminals of said add-one register and output terminals connected to the input terminals of said program address register, input terminals of said add-one register connected via gating circuits to said central control unmasked bus and to said central control masked bus, said output conductors of said add-one circuit connected to said masked bus via gating circuits, and means responsive to said program order words for generating control signals for enabling said add-one circuit and said gating circuits.

Claim 42

In combination, a memory, sequences of program order words, and a central control, said central control comprising a masked bus, an unmasked bus, means for generating code-addresses for obtaining program order words from said memory, said means including a program address register, means for transmitting said code-addresses to said memory, and means for incrementing said code-addresses by a count of 1, said means for incrementing comprising an add-one register having input terminals connected to the output terminals of said program address register, an add-one circuit having input terminals connected to the output terminals of said add-one register and output terminals connected to the input terminals of said program address register, input terminals of said add-one register connected via gating circuits to said central control unmasked bus and to said central control masked bus, said output conductors of said add-one circuit connected to said masked bus via gating circuits, and means responsive to said program order words for generating control signals for enabling said add-one circuit and said gating circuits.

Claim 43

A program-controlled data processor comprising a program store, a data store, a central control including a masked bus and an unmasked bus, a program address register, means for transmitting the contents of said program address register to said program store to obtain information therefrom, means in said central control defining a basic machine cycle, a plurality of phases within said machine cycle, and a plurality of distinct times within each of said phases, said central control further comprising means defining an order operational step period, said operational step period extending beyond one machine cycle, means connected to the output terminals of said program address register for incrementing the code-address stored therein by a count of 1, said means effective during a first portion of said operational step period, means connecting said unmasked bus and said masked bus of the central control to both the input terminals and the output terminals of said incrementing circuit, and control means effective to gate information from said unmasked bus and said masked bus to said incrementing circuit and from said incrementing circuit to said unmasked bus and said masked bus during a second subsequent time in said operational step period.

Claim 44

A program-controlled data processor comprising a program store, a data store, a central control including a masked bus and an unmasked bus, a program address register, means for transmitting the contents of said program address register to said program store to obtain information therefrom, means in said central control defining a basic machine cycle, a plurality of phases within said machine cycle, and a plurality of distinct times within each of said phases, said central control further comprising means defining an order operational step period, said operational step period extending beyond one machine cycle, means connected to the output terminals of said program address register for incrementing the code-address stored therein by a count of 1, said means effective during a first portion of said operational step period, means connecting said unmasked bus and said masked bus of the central control to both the input terminals and the output terminals of said incrementing circuit, and control means effective to gate information from said unmasked bus and said masked bus to said incrementing circuit and from said incrementing circuit to said unmasked bus and said masked bus during a second subsequent time in said operational step period.

Claim 45

In combination, a program store containing sequences of program order words, certain of said order words representing single cycle orders and others of said order words representing multicycle orders; a central control comprising means for reading information from said program store, clock means defining a central control machine cycle, phases within said cycle and times within said phases, a buffer order word register, means for transferring information from said program store to said buffer order word register, a buffer order word decoder responsive to the contents of said buffer order word register for controlling portions of said central control, an order word register, means for transmitting the contents of said buffer order word register to said order word register at a distinct time in said machine cycle, an order word decoder responsive to the contents of said order word register for controlling portions of said central control, and sequencer means responsive to sequencer enable output signals of said order word decoder for causing said central cOntrol to perform selected repeated central control work functions, said sequencer means effective to control portions of said central control beyond the period of time that the order which enabled said sequencer resides in said order word register.

Claim 46

In combination, a program store containing sequences of program order words, certain of said order words representing single cycle orders and others of said order words representing multicycle orders; a central control comprising means for reading information from said program store, clock means defining a central control machine cycle, phases within said cycle and times within said phases, a buffer order word register, means for transferring information from said program store to said buffer order word register, a buffer order word decoder responsive to the contents of said buffer order word register for controlling portions of said central control, an order word register, means for transmitting the contents of said buffer order word register to said order word register at a distinct time in said machine cycle, an order word decoder responsive to the contents of said order word register for controlling portions of said central control, and sequencer means responsive to sequencer enable output signals of said order word decoder for causing said central cOntrol to perform selected repeated central control work functions, said sequencer means effective to control portions of said central control beyond the period of time that the order which enabled said sequencer resides in said order word register.

Claim 47

The combination in accordance with claim 29 wherein said central control further comprises operational checking means for checking the validity of the contents of said buffer order word register and for generating a trouble signal on detection of invalid contents, remedial means responsive to said trouble signals for carrying out remedial work functions, said remedial means generates output signals for inhibiting the transmitting of the contents of said buffer order word register to said order word register and to inhibit the operation of said buffer order word decoder and said order word decoder.

Claim 48

The combination in accordance with claim 29 wherein said central control further comprises operational checking means for checking the validity of information obtained from said data store and for generating trouble signals upon detection of invalid information, remedial means responsive to said trouble signals for carrying out remedial work functions, said remedial means generates output signals for inhibiting the operation of said buffer order word decoder and said order word decoder and for inhibiting the transmitting of the contents of the said buffer order word register to said order word register.

Claim 49

A program-controlled data-processor system comprising an input-output system, a program store containing sequences of program order words, certain of said order words, including input-output command orders, representing single cycle orders and other of said order words representing multicycle orders, a data store, a central control comprising means for reading information from said program store and from said data store, means responsive to said input-output command program order words for generating input-output commands for controlling said input-output system, said central control comprising instruction registers and decoder means concurrently operative with respect to three successive single-cycle program-order words with a fixed degree of operational overlap between successive orders, said means for generating input-output commands comprises an input-output command sequencer means which extends the data processing time for input-output command program orders beyond a period of time required to execute other single-cycle orders and thereby extends the degree of operational overlap between an input-output command order and succeeding orders.

Claim 50

A program-controlled data-processor system comprising an input-output system, a program store containing sequences of program order words, certain of said order words, including input-output command orders, representing single cycle orders and other of said order words representing multicycle orders, a data store, a central control comprising means for reading information from said program store and from said data store, means responsive to said input-output command program order words for generating input-output commands for controlling said input-output system, said central control comprising instruction registers and decoder means concurrently operative with respect to three successive single-cycle program-order words with a fixed degree of operational overlap between successive orders, said means for generating input-output commands comprises an input-output command sequencer means which extends the data processing time for input-output command program orders beyond a period of time required to execute other single-cycle orders and thereby extends the degree of operational overlap between an input-output command order and succeeding orders.

Claim 51

A program-controlled data-processor system comprising an input-output system, a program store containing sequences of program order words, certain of said order words, including input-output command order words, representing single-cycle orders and other of said order words representing multicycle orders, a central control comprising means for reading information from said program store and from said data store, clock means defining a central control machine cycle, phases within said cycle, and times within said phases, a buffer order word register, means for transmitting information read from said program store to said buffer order word register, a buffer order word decoder responsive to the contents of said buffer order word register for controlling portions of said central control, an order word register, means for transmitting the contents of said buffer order word register to said order word register at a distinct time in said machine cycle, an order word decoder responsive to the contents of said order word register, an input-output command sequencer responsive to enable output signals of said order word decoder for generating input-output commands for controlling said input-output system, said input-output command sequencer eFfective to control portions of said central control beyond the period of time that the succeeding program order word resides in said buffer order word register.

Claim 52

A program-controlled data-processor system comprising an input-output system, a program store containing sequences of program order words, certain of said order words, including input-output command order words, representing single-cycle orders and other of said order words representing multicycle orders, a central control comprising means for reading information from said program store and from said data store, clock means defining a central control machine cycle, phases within said cycle, and times within said phases, a buffer order word register, means for transmitting information read from said program store to said buffer order word register, a buffer order word decoder responsive to the contents of said buffer order word register for controlling portions of said central control, an order word register, means for transmitting the contents of said buffer order word register to said order word register at a distinct time in said machine cycle, an order word decoder responsive to the contents of said order word register, an input-output command sequencer responsive to enable output signals of said order word decoder for generating input-output commands for controlling said input-output system, said input-output command sequencer eFfective to control portions of said central control beyond the period of time that the succeeding program order word resides in said buffer order word register.

Claim 53

A program-controlled data-processor system comprising an input-output system, a program store containing sequences of program order words, certain of said order words, including input-output command order words, representing single cycle orders and other of said order words representing multicycle orders, a central control comprising clock means defining a central-control machine cycle, phases within said cycle, and times within said phases, means for reading program order words from said program store at fixed times within each successive machine cycle, a buffer order word register for receiving program order words read from said program store, a buffer order word decoder responsive to the contents of said buffer order word register for controlling a portion of said central control, an order word register, means for transferring the contents of said buffer order word register to said order word register at a second fixed time in each successive machine cycle, an order word decoder responsive to the contents of said order word register, an input-output command sequencer, said order word decoder responsive to the occurrence of an input-output command order in said order word register for generating an input-output command sequencer enable signal, said input-output command sequencer effective when enabled to generate input-output commands for controlling said input-output system, said input-output command sequencer operative beyond said second fixed time of machine cycles immediately following the cycle in which the input-output command order occurred in said order word register.

Claim 54

A program-controlled data-processor system comprising an input-output system, a program store containing sequences of program order words, certain of said order words, including input-output command order words, representing single cycle orders and other of said order words representing multicycle orders, a central control comprising clock means defining a central-control machine cycle, phases within said cycle, and times within said phases, means for reading program order words from said program store at fixed times within each successive machine cycle, a buffer order word register for receiving program order words read from said program store, a buffer order word decoder responsive to the contents of said buffer order word register for controlling a portion of said central control, an order word register, means for transferring the contents of said buffer order word register to said order word register at a second fixed time in each successive machine cycle, an order word decoder responsive to the contents of said order word register, an input-output command sequencer, said order word decoder responsive to the occurrence of an input-output command order in said order word register for generating an input-output command sequencer enable signal, said input-output command sequencer effective when enabled to generate input-output commands for controlling said input-output system, said input-output command sequencer operative beyond said second fixed time of machine cycles immediately following the cycle in which the input-output command order occurred in said order word register.

Claim 55

In combination, a program store containing sequences of program order words, a data store, a central control comprising means for reading information from each of said stores, decoding means responsive to program order words read from said program store for controlling said central control, clock means defining central control machine cycles, said decoding means responsive to each of said program order words for an operational step period of time, said operational step period being longer than one machine cycle and comprising two distinct time periods, checking means in said central control responsive to program order words read from said program store for checking the plausibility of program store responses, said checking means operative to generate error signals upon detection of an implausible response, sequencer means responsive to said error signals for interrupting the operation of said decoding means during the indexing cycle of the operational step of an order word which the checking circuit indicated as implausible, said sequencer effective to generate a command for rereading said program store at the address from which the implausible response was obtained, and means for returning control of central control to said decoding means.

Claim 56

In combination, a program store containing sequences of program order words, a data store, a central control comprising means for reading information from each of said stores, decoding means responsive to program order words read from said program store for controlling said central control, clock means defining central control machine cycles, said decoding means responsive to each of said program order words for an operational step period of time, said operational step period being longer than one machine cycle and comprising two distinct time periods, checking means in said central control responsive to program order words read from said program store for checking the plausibility of program store responses, said checking means operative to generate error signals upon detection of an implausible response, sequencer means responsive to said error signals for interrupting the operation of said decoding means during the indexing cycle of the operational step of an order word which the checking circuit indicated as implausible, said sequencer effective to generate a command for rereading said program store at the address from which the implausible response was obtained, and means for returning control of central control to said decoding means.

Claim 57

In combination, a program store containing sequences of program order words, a central control, means in said central control for generating code-addresses for sequentially reading order words from said program store at regular intervals, checking means responsive to program order words read from said program store, said checking means generates an error signal upon detection of an error in one of said program order words, means responsive to said error signal for momentarily interrupting said sequential obtaining of program order words, said interrupting means including means for generating and transmitting a code-address corresponding to the code-address of the program order word in which an error was detected.

Claim 58

In combination, a program store containing sequences of program order words, a central control, means in said central control for generating code-addresses for sequentially reading order words from said program store at regular intervals, checking means responsive to program order words read from said program store, said checking means generates an error signal upon detection of an error in one of said program order words, means responsive to said error signal for momentarily interrupting said sequential obtaining of program order words, said interrupting means including means for generating and transmitting a code-address corresponding to the code-address of the program order word in which an error was detected.

Claim 59

In combination, a program store containing sequences of program order words, certain of saId order words being transfer order words, a data store containing system data, a central control for obtaining information from said stores, for writing information into said data store, and for executing said sequences of program order words, means responsive to the execution of said transfer orders for generating transfer signals and advance signals, and transfer means responsive to said transfer signals for obtaining a data word defining the order to be transferred to, said last-named means including means for obtaining information from said program store or from said data store as specified by a portion of said transfer order.

Claim 60

In combination, a program store containing sequences of program order words, certain of saId order words being transfer order words, a data store containing system data, a central control for obtaining information from said stores, for writing information into said data store, and for executing said sequences of program order words, means responsive to the execution of said transfer orders for generating transfer signals and advance signals, and transfer means responsive to said transfer signals for obtaining a data word defining the order to be transferred to, said last-named means including means for obtaining information from said program store or from said data store as specified by a portion of said transfer order.

Claim 61

The combination in accordance with claim 37 wherein said transfer means comprises a transfer sequencer which momentarily inhibits output signals of said decoding means and generates output signals which cause said central control to selectively obtain information from said program store or from said data store.

Claim 62

The combination in accordance with claim 38 wherein said central control further comprises a plurality of flip-flop registers, said transfer sequencer further comprises means for generating signals for selectively modifying the contents of a selected one of certain of said flip-flop registers as determined by a portion of said transfer order word.

Claim 63

In combination, a program store containing sequences of program order words and data, a data store containing system data; a central control comprising means for obtaining information from said stores and means for writing information into said data store, executing means responsive to said sequences of program order words, an order word register, a data register, transmission means interconnecting said data store and said central control, and gating means for selectively gating information from said transmission means to said data register and to said order word register, said executing means including means for generating gate control signals for selectively transmitting said data to said data register and to said order word register.

Claim 64

In combination, a program store containing sequences of program order words and data, a data store containing system data; a central control comprising means for obtaining information from said stores and means for writing information into said data store, executing means responsive to said sequences of program order words, an order word register, a data register, transmission means interconnecting said data store and said central control, and gating means for selectively gating information from said transmission means to said data register and to said order word register, said executing means including means for generating gate control signals for selectively transmitting said data to said data register and to said order word register.

Claim 65

In combination, a central data processor comprising a program store containing sequences of program order words, certain of said order words being data processing-transfer order words, a data store containing system data, a central control comprising means for obtaining information from said stores, means for writing data into said data store, data processing means, and decoding means responsive to said sequences of program order words; said decoding means responsive to said data processing-transfer order words for generating control signals for carrying out specified data processing actions in said data processing means and for generating transfer control signals, and transfer means responsive to output signals of said data processing means resulting from said specified data processing action and to said transfer control signals for generating system advance and system transfer signals.

Claim 66

In combination, a central data processor comprising a program store containing sequences of program order words, certain of said order words being data processing-transfer order words, a data store containing system data, a central control comprising means for obtaining information from said stores, means for writing data into said data store, data processing means, and decoding means responsive to said sequences of program order words; said decoding means responsive to said data processing-transfer order words for generating control signals for carrying out specified data processing actions in said data processing means and for generating transfer control signals, and transfer means responsive to output signals of said data processing means resulting from said specified data processing action and to said transfer control signals for generating system advance and system transfer signals.

Claim 67

In combination, a program store containing sequences of program order words and data, said program store in response to commands generates 44-bit responses, each of said responses including a 7-bit Hamming error check field; a central control comprising means for generating commands for obtaining information from said program store, an order word register for storing responses from said program store, an order word decoder connected to an operation field portion of said order word register, an index adder system comprising an index adder, an index adder addend register, an index adder augend register, gating means interconnecting said order word register and said index adder addend register, and means for generating control signals for said gating means, said gating means comprising means for selectively: a. transmitting the contents of the fIrst 23 bits of said order word register to said addend register without modification, b. for transmitting the first 21 bits of said order word register to said addend register, expanding bit 21 to provide a 23-bit word in said addend register, c. transmitting bits 21 through 36 of said order word register to said addend register without modification, and d. transmitting bits 41 through 43 of said order word register to said addend register without modification.

Claim 68

In combination, a program store containing sequences of program order words and data, said program store in response to commands generates 44-bit responses, each of said responses including a 7-bit Hamming error check field; a central control comprising means for generating commands for obtaining information from said program store, an order word register for storing responses from said program store, an order word decoder connected to an operation field portion of said order word register, an index adder system comprising an index adder, an index adder addend register, an index adder augend register, gating means interconnecting said order word register and said index adder addend register, and means for generating control signals for said gating means, said gating means comprising means for selectively: a. transmitting the contents of the fIrst 23 bits of said order word register to said addend register without modification, b. for transmitting the first 21 bits of said order word register to said addend register, expanding bit 21 to provide a 23-bit word in said addend register, c. transmitting bits 21 through 36 of said order word register to said addend register without modification, and d. transmitting bits 41 through 43 of said order word register to said addend register without modification.

Claim 69

In combination, a program store containing sequences of program order words and data; a central control comprising means for generating commands for obtaining information from said program store, an order word register for storing information obtained from said program store, order word decoding means, an index-adder system, gating means interposed between said order word register and said index-adder system, and means for generating control signals for said gating means, said gating means comprising means for selectively: a. transmitting without modification selected portions of the contents of said order word register to said index adder system, and b. transmitting a selected portion of the contents of said order word register with one bit of said portion expanded to provide a data word having more bits than said portion.

Claim 70

In combination, a program store containing sequences of program order words and data; a central control comprising means for generating commands for obtaining information from said program store, an order word register for storing information obtained from said program store, order word decoding means, an index-adder system, gating means interposed between said order word register and said index-adder system, and means for generating control signals for said gating means, said gating means comprising means for selectively: a. transmitting without modification selected portions of the contents of said order word register to said index adder system, and b. transmitting a selected portion of the contents of said order word register with one bit of said portion expanded to provide a data word having more bits than said portion.

Claim 71

In combination, a program store containing sequences of program order words and system data, certain of said order words being memory reading control order words, a data store containing system data, a central control comprising means for obtaining information from said stores and for writing data into said data store, means for executing said sequences of program order words, a control decision register, a data buffer register for storing information obtained from said stores, gating means for transmitting a portion of the contents of said data buffer register to said control decision register, means responsive to the execution of said memory reading control order words to generate control signals to enable said gating means, and decision logic responsive to certain of said order words and the states of said control decision register for generating transfer signals and advance signals.

Claim 72

In combination, a program store containing sequences of program order words and system data, certain of said order words being memory reading control order words, a data store containing system data, a central control comprising means for obtaining information from said stores and for writing data into said data store, means for executing said sequences of program order words, a control decision register, a data buffer register for storing information obtained from said stores, gating means for transmitting a portion of the contents of said data buffer register to said control decision register, means responsive to the execution of said memory reading control order words to generate control signals to enable said gating means, and decision logic responsive to certain of said order words and the states of said control decision register for generating transfer signals and advance signals.

Claim 73

In combination, a memory-containing sequences of program order words and system data, a central control comprising means for reading information from said memory and for writing data into said memory, means for executing said program sequences, an unmasked bus, a masked bus, first gating means interposed between said unmasked bus and said masked bus, a plurality of data sources, a plurality of data destinations, and means responsive to the execution of said sequences of program order words to simultaneously gate information from a selected data source to a selected data destination via said masked bus and to gate other information from a second selected data source to a second selected data destination via said unmasked bus.

Claim 74

In combination, a memory-containing sequences of program order words and system data, a central control comprising means for reading information from said memory and for writing data into said memory, means for executing said program sequences, an unmasked bus, a masked bus, first gating means interposed between said unmasked bus and said masked bus, a plurality of data sources, a plurality of data destinations, and means responsive to the execution of said sequences of program order words to simultaneously gate information from a selected data source to a selected data destination via said masked bus and to gate other information from a second selected data source to a second selected data destination via said unmasked bus.

Claim 75

A processor to provide processing of present and anticipated instructions, said processor comprising: a. an instruction executing final station means, b. means for processing instructions prior to their arrival at said final station, c. means for determining before execution of an instruction whether a branch or other occurrence will be effected which would make preprocessing steps and manipulation of data undesirable to be executed, and d. means responsive to said determining means for preventing further preprocessing by said prior processing means.

Claim 76

A processor to provide processing of present and anticipated instructions, said processor comprising: a. an instruction executing final station means, b. means for processing instructions prior to their arrival at said final station, c. means for determining before execution of an instruction whether a branch or other occurrence will be effected which would make preprocessing steps and manipulation of data undesirable to be executed, and d. means responsive to said determining means for preventing further preprocessing by said prior processing means.

Claim 77

The processor of claim 46, said determining means comprising an advance station control and jump control means operating in conjunction and responsive in accordance with results of a conditional jump operation where present in said anticipated instructions to decide and impLement a decision selectively to allow processing in said final station and to prevent processing in said final station.