Pcm transmission system

Claim 2

A transmitter for sending an analog signal varying in magnitude as a pulse code modulation signal compressed in band width, comprising: a source of an analog signal varying in magnitude; a generator of timing signals having different repetitive times; means activated by successive clock signals occuring at a repetitive sampling time t for encoding one portion of said analog signal into a first preselected number of first sets, each consisting of a first preassigned number of parallel pulse code modulation pulses containing most significant digits and least significant digits and corresponding to one sample of said analog signal; means for compressing said first sets in bandwidth; means for transmitting said first sets as compressed in bandwidth; and means for activating said compressing means to control the bandwidth compression of said first sets and simultaneously therewith to sense the speed of variation in magnitude between successive first sets and thereby between corresponding successive analog signal samples, including: means activated by a second portion of said analog signal and a further timing signal occurring at a repetitive time 2t for producing ''''1'''' and ''''0'''' logic signals to indicate rapid and slow rates of speed variation, respectively, in the magnitude of said analog signal at successive even number first sets and thereby at corresponding successive even number analog signal samples; and circuit means for applying to said compressing means said ''''1'''' and ''''0'''' logic signals and a predetermined number of additional timing sIgnals of which one occurs at said sampling time t and others occur at a time 2t to compress said first pulse sets into a preselected number of second sets of parallel pulse code modulation pulses; said second preselected number being less than said first preselected number; whereby each set of said second sets is provided with said more significant digits of one odd number of said first sets; certain sets of said second sets are provided with said more significant digits thereof combined with said less significant digits of corresponding odd number first sets as slow speed variations occur in the magnitude of said analog signal at even number first sets next adjacent to said respective lastmentioned odd number first sets; other sets of said second sets are provided with said more significant digits of corresponding other odd number first sets combined with said more significant digits of other even number first sets as rapid speed variations occur in the magnitude of said analog signal at other even number first sets next adjacent to said lastmentioned other odd number first sets; and final digits comprising ''''0'''' and ''''1'''' logic signals are provided in said certain and other second sets to indicate said slow and rapid variations, respectively, in said analog signal magnitude at said respective even number first sets.

Claim 3

The transmitter according to claim 1 in which said control means includes means responsive to said analog signal second portion for deriving therefrom a signal varying in magnitude and representing a varying difference in magnitude between a true value and a calculated value of said last-mentioned portion, thereby to sense said rapid and slow variations in said analog signal magnitude.

Claim 4

The transmitter according to claim 2 in which said control means includes: a source of threshold voltage having a fixed magnitude; and means for comparing the magnitude of said derived difference voltage and said threshold voltage magnitude at successive times 2t corresponding to said first-mentioned and other even number first sets to produce said ''''0'''' and ''''1'''' logic signals.

Claim 5

A transmitter for an analog signal varying in magnitude as a pulse code modulation signal compressed in bandwidth, comprising: a source of an analog signal varying in magnitude; a generator of timing signals having different repetitive times; means activated by predetermined number of successive timing signals occurring at repetitive sampling times t for encoding one portion of said analog signal into a preselected number of first sets, each consisting of a first preassigned number of parallel pulse code modulation pulses containing more significant digits and less significant digits and corresponding to one sample of said analog signal; means for compressing said first sets in bandwidth; means for transmitting said first sets as compressed in bandwidth; and means for activating said compressing means to control the bandwidth compression of said first sets and simultaneously therewith to sense the speed variation in magnitude between successive first sets and thereby between corresponding successive analog signal samples, including: means responsive to a second portion of said analog signal for deriving therefrom a signal varying in magnitude and representing a varying difference in magnitude between a true value and a calculated value of said last-mentioned portion thereby to sense the speed variation in the magnitude of said analog signal at successive first sets and thereby at corresponding successive analog signal samples; a source of threshold voltage of fixed magnitude; means for comparing the magnitudes of said derived voltage and said threshold voltage at successive timing signals 2t corresponding to successive even numbers of said first sets to produce two different logic signals to represent the speed variation in the magnitude at said last-mentioned eVen number first sets, a first of said two logic signals representing a slow speed variation magnitude and a second of said two logic signals representing a rapid speed variation magnitude, each of said one and other logic signals having a time duration 2t; means for delaying said first and second logic signals to register in time with two successive first sets, each including one of said even number first sets; and circuit means for applying to said compressing means and first and second speed variation logic signals and a predetermined number of additional timing pulses of which one occurs at said sampling time t and others occur at a time 2t to compress said first sets into a preselected number of second sets, each consisting of a second preassigned number of parallel pulse code modulation pulses and one of said first and second logic signals; said second preselected number being less than said first preselected number; whereby each of said second sets includes said more significant digits of one odd number of said first sets; each of said last-mentioned digits doubled in width and delayed by one sampling time t relative to said respective first and second speed-variation logic signals; certain sets of said second sets are provided with said more significant digits thereof combined said less significant digits of corresponding odd number first sets as slow speed variations occur in the magnitude of said analog signal at even number first sets adjacent to said last-mentioned odd number first sets as indicated by said first logic signals; each of said last-mentioned less significant digits doubled in width and delayed by one sampling time t; and other sets of said second sets are provided with said more significant digits of corresponding other odd number first sets combined with said more significant digits of other even number first sets as rapid speed variations occur in the magnitude of said analog signal at other even number first sets next adjacent to said last-mentioned odd number first sets; and final digits comprising ''''0'''' and ''''1'''' logic signals corresponding to said first and second speed variation signals, respectively, are provided in said certain and other second sets to indicate said respective slow and rapid variations in said analog signal magnitude at said respective even number first sets.

Claim 6

A transmitter for an analog signal varying in magnitude as a pulse code modulation signal compressed in bandwidth, comprising: a source of an analog signal varying in magnitude; a generator of timing signals having different repetitive times; means activated by predetermined number of successive timing signals occurring at repetitive sampling times t for encoding one portion of said analog signal into a preselected number of first sets, each consisting of a first preassigned number of parallel pulse code modulation pulses containing more significant digits and less significant digits and corresponding to one sample of said analog signal; means for compressing said first sets in bandwidth; means for transmitting said first sets as compressed in bandwidth; and means for activating said compressing means to control the bandwidth compression of said first sets and simultaneously therewith to sense the speed variation in magnitude between successive first sets and thereby between corresponding successive analog signal samples, including: means responsive to a second portion of said analog signal for deriving therefrom a signal varying in magnitude and representing a varying difference in magnitude between a true value and a calculated value of said last-mentioned portion thereby to sense the speed variation in the magnitude of said analog signal at successive first sets and thereby at corresponding successive analog signal samples; a source of threshold voltage of fixed magnitude; means for comparing the magnitudes of said derived voltage and said threshold voltage at successive timing signals 2t corresponding to successive even numbers of said first sets to produce two different logic signals to represent the speed variation in the magnitude at said last-mentioned eVen number first sets, a first of said two logic signals representing a slow speed variation magnitude and a second of said two logic signals representing a rapid speed variation magnitude, each of said one and other logic signals having a time duration 2t; means for delaying said first and second logic signals to register in time with two successive first sets, each including one of said even number first sets; and circuit means for applying to said compressing means and first and second speed variation logic signals and a predetermined number of additional timing pulses of which one occurs at said sampling time t and others occur at a time 2t to compress said first sets into a preselected number of second sets, each consisting of a second preassigned number of parallel pulse code modulation pulses and one of said first and second logic signals; said second preselected number being less than said first preselected number; whereby each of said second sets includes said more significant digits of one odd number of said first sets; each of said last-mentioned digits doubled in width and delayed by one sampling time t relative to said respective first and second speed-variation logic signals; certain sets of said second sets are provided with said more significant digits thereof combined said less significant digits of corresponding odd number first sets as slow speed variations occur in the magnitude of said analog signal at even number first sets adjacent to said last-mentioned odd number first sets as indicated by said first logic signals; each of said last-mentioned less significant digits doubled in width and delayed by one sampling time t; and other sets of said second sets are provided with said more significant digits of corresponding other odd number first sets combined with said more significant digits of other even number first sets as rapid speed variations occur in the magnitude of said analog signal at other even number first sets next adjacent to said last-mentioned odd number first sets; and final digits comprising ''''0'''' and ''''1'''' logic signals corresponding to said first and second speed variation signals, respectively, are provided in said certain and other second sets to indicate said respective slow and rapid variations in said analog signal magnitude at said respective even number first sets.

Claim 7

A transmitter for sending an analog signal varying in magnitude as a pulse code modulation signal, comprising: a source of analog signal varying in magnitude; means for encoding a first portion of said analog signal into a preselected number of first sets of parallel pulse code modulation pulses, each set representing a corresponding sample of said analog signal and including a first preassigned number of said parallel pulses including more significant digits and less significant digits; means activated by a second portion of said analog signal for compressing said first pulse sets into a second preselected number of second sets of parallel pulse code modulation pulses; said second preselected number being smaller than said first preselected number; each set of said second pulse sets including said more significant digits of one odd number set of said first sets; certain sets of said second pulse sets having said more significant digits thereof combined with said less significant digits of corresponding odd number first sets as slow speed variations occur in the magnitude of said analog signal at even number first sets next adjacent to said respective last-mentioned odd number first sets; other sets of said second sets having said more significant digits of corresponding other odd number first sets combined with said more significant digits of other even number first sets as rapid speed variation occurs in the magnitude of said analog signal at other even number first sets next adjacent to said last-mentioned other odd number first sets; and a final digit included in each of said certain second sets and comprising a ''''0'''' logic signal to indicate said slow variation analog signal magnitude at each of said first-mentioned even number first sets and a ''''1'''' logic signal in each of said other second sets to indicate said rapid variation analog signal magnitude at each of said other even number first sets; and means for transmitting said second sets of parallel pulse code modulation pulses

Claim 8

A transmitter for sending an analog signal varying in magnitude as a pulse code modulation signal, comprising: a source of analog signal varying in magnitude; means for encoding a first portion of said analog signal into a preselected number of first sets of parallel pulse code modulation pulses, each set representing a corresponding sample of said analog signal and including a first preassigned number of said parallel pulses including more significant digits and less significant digits; means activated by a second portion of said analog signal for compressing said first pulse sets into a second preselected number of second sets of parallel pulse code modulation pulses; said second preselected number being smaller than said first preselected number; each set of said second pulse sets including said more significant digits of one odd number set of said first sets; certain sets of said second pulse sets having said more significant digits thereof combined with said less significant digits of corresponding odd number first sets as slow speed variations occur in the magnitude of said analog signal at even number first sets next adjacent to said respective last-mentioned odd number first sets; other sets of said second sets having said more significant digits of corresponding other odd number first sets combined with said more significant digits of other even number first sets as rapid speed variation occurs in the magnitude of said analog signal at other even number first sets next adjacent to said last-mentioned other odd number first sets; and a final digit included in each of said certain second sets and comprising a ''''0'''' logic signal to indicate said slow variation analog signal magnitude at each of said first-mentioned even number first sets and a ''''1'''' logic signal in each of said other second sets to indicate said rapid variation analog signal magnitude at each of said other even number first sets; and means for transmitting said second sets of parallel pulse code modulation pulses

Claim 9

A receiver for a pulse code modulation signal comprised in bandwidth to represent an analog signal, comprising: a source of output series pulse code modulation pulses compressed in bandwidth to represent an analog signal varying in magnitude and divided into a preselected number of first sets of parallel pulse code modulation pulses, each set representing a corresponding sample of said analog signal and including a first preassigned number of said parallel pulses consisting of more significant digits and less significant digits; said pulses of said first sets compressed into a preselected number of second sets of parallel pulse code modulation pulses; said preselected first set number being greater than said preselected second set number; each set of said second sets including said more significant digits of one number set of said first sets; certain sets of said second sets having said more significant digits thereof combined with said less significant digits of corresponding odd number first sets as slow speed variations occur in the magnitude of said analog signal at next adjacent even number first sets; other sets of said second sets including said more significant digits of corresponding other odd number first sets combined with said more significant digits of next adjacent other even number first sets as rapid speed variations occur in the magnitude of said analog signal at said last-mentioned sets; and final digits included in said respective second sets and comprising ''''0'''' and ''''1'''' logic signals to indicate said slow and rapid variation analog signal magnitudes, respectively, at each of said first-mentioned even number first sets; each of said digits in each of said second sets and said respective ''''0'''' and ''''1'''' signals having a time duration of 2t, t being the time of each of said analog signal samples; leading edges of said second set digits including said combined more significant and less significant digits corresponding with leading edges of associated ''''0'''' signals and leading edges of said second set digits including said combined more significant digits corresponding with leading edges of associated ''''1'''' signals; said second set parallel pulse digits present at said source output as corresponding series pulse code modulation pulses; means for generating a first timing pulse recurring at a time 4t, a second timing pulse recurring at a time 2t, and third and fourth timing pulses, each recurring at a time t; means activated by said first timing pulses for converting said source output preselected second set series pulse code modulation pulses into a preselected number of third sets of pulse code modulation pulses of combined parallel more significant digits, less significant digits, and ''''0'''' and ''''1'''' logic signals corresponding to said combined more significant digits, less significant digits, and said ''''0'''' and ''''1'''' signals, respectively, of said preselected second pulse sets; means responsive to said second, third and fourth timing pulses for rearranging said third pulse sets to provide a preselected number of fourth sets of parallel pulse code modulation pulses; said preselected fourth number being greater than said preselected first number; certain sets of said fourth sets provided with combined parallel more significant digits and less significant digits corresponding to said odd number first pulse sets consisting of more significant digits and less significant digits during first halves of said respectIve second timing pulses 2t and followed by sets of parallel ''''0'''' logic signals during the second halves of said last-mentioned pulses when said final pulses in said respective third pulse sets are ''''0'''' logic signals; and other sets of said fourth pulse sets provided with more significant digits corresponding to said more significant digits of other odd number first pulse sets during first halves of said respective second timing pulses 2t and followed by more significant digits corresponding to said more significant digits of said other next adjacent even number first pulse sets during second halves of said last-mentioned pulses when said final pulses in said respective other third sets are logic ''''1'''' signals; said parallel more significant digits in said respective other fourth sets followed by parallel sequential sets of ''''1,'''' ''''0'''' and ''''1'''' logic signals; and means for utilizing said fourth pulse sets to reproduce said analog signal varying in magnitude.

Claim 10

A receiver for a pulse code modulation signal comprised in bandwidth to represent an analog signal, comprising: a source of output series pulse code modulation pulses compressed in bandwidth to represent an analog signal varying in magnitude and divided into a preselected number of first sets of parallel pulse code modulation pulses, each set representing a corresponding sample of said analog signal and including a first preassigned number of said parallel pulses consisting of more significant digits and less significant digits; said pulses of said first sets compressed into a preselected number of second sets of parallel pulse code modulation pulses; said preselected first set number being greater than said preselected second set number; each set of said second sets including said more significant digits of one number set of said first sets; certain sets of said second sets having said more significant digits thereof combined with said less significant digits of corresponding odd number first sets as slow speed variations occur in the magnitude of said analog signal at next adjacent even number first sets; other sets of said second sets including said more significant digits of corresponding other odd number first sets combined with said more significant digits of next adjacent other even number first sets as rapid speed variations occur in the magnitude of said analog signal at said last-mentioned sets; and final digits included in said respective second sets and comprising ''''0'''' and ''''1'''' logic signals to indicate said slow and rapid variation analog signal magnitudes, respectively, at each of said first-mentioned even number first sets; each of said digits in each of said second sets and said respective ''''0'''' and ''''1'''' signals having a time duration of 2t, t being the time of each of said analog signal samples; leading edges of said second set digits including said combined more significant and less significant digits corresponding with leading edges of associated ''''0'''' signals and leading edges of said second set digits including said combined more significant digits corresponding with leading edges of associated ''''1'''' signals; said second set parallel pulse digits present at said source output as corresponding series pulse code modulation pulses; means for generating a first timing pulse recurring at a time 4t, a second timing pulse recurring at a time 2t, and third and fourth timing pulses, each recurring at a time t; means activated by said first timing pulses for converting said source output preselected second set series pulse code modulation pulses into a preselected number of third sets of pulse code modulation pulses of combined parallel more significant digits, less significant digits, and ''''0'''' and ''''1'''' logic signals corresponding to said combined more significant digits, less significant digits, and said ''''0'''' and ''''1'''' signals, respectively, of said preselected second pulse sets; means responsive to said second, third and fourth timing pulses for rearranging said third pulse sets to provide a preselected number of fourth sets of parallel pulse code modulation pulses; said preselected fourth number being greater than said preselected first number; certain sets of said fourth sets provided with combined parallel more significant digits and less significant digits corresponding to said odd number first pulse sets consisting of more significant digits and less significant digits during first halves of said respectIve second timing pulses 2t and followed by sets of parallel ''''0'''' logic signals during the second halves of said last-mentioned pulses when said final pulses in said respective third pulse sets are ''''0'''' logic signals; and other sets of said fourth pulse sets provided with more significant digits corresponding to said more significant digits of other odd number first pulse sets during first halves of said respective second timing pulses 2t and followed by more significant digits corresponding to said more significant digits of said other next adjacent even number first pulse sets during second halves of said last-mentioned pulses when said final pulses in said respective other third sets are logic ''''1'''' signals; said parallel more significant digits in said respective other fourth sets followed by parallel sequential sets of ''''1,'''' ''''0'''' and ''''1'''' logic signals; and means for utilizing said fourth pulse sets to reproduce said analog signal varying in magnitude.

Claim 11

The receiver according to claim 6 in which said utilizing means includes: means for delaying a first portion of said fourth pulse sets by a first 1-digit time interval; and means for delaying a first portion of said 1-digit delayed first portion of said fourth pulse sets by a second 1-digit time interval.

Claim 12

The receiver according to claim 7 in which: said timing means generates a fifth timing pulse recurring at a time 2t; and said utilizing means comprises means responsive to said ''''0'''' and ''''1'''' signals included in said third pulse sets and to said fifth timing pulse for digitally adding a second portion of said fourth pulse sets and said first portion of said fourth pulse sets delayed by said first and second 1-digit time intervals and thereafter dividing such digital sum by two to produce a fifth preselected number of means sets of parallel pulse modulation pulses, said first and fifth preselected numbers being identical; said fifth pulse sets comprising sets of ''''0'''' logic signals corresponding to said certain and other sets included in said fourth pulse sets and further sets of combined more significant and less significant digits corresponding to sets of parallel ''''0'''' signals included in said fourth pulse sets.

Claim 13

The receiver according to claim 8 in which: said timing means generates sixth and seventh timing pulses, each recurring at a time t; said utilizing means comprises means responsive to said sixth and seventh timing pulses for superposing said fifth pulse sets on a second portion of said 1-digit delayed first portion of said fourth pulse sets to produce a sixth preselected number of sets parallel pulse code modulation pulses; said first and sixth preselected numbers being identical; certain sets of said sixth pulse sets comprising combined more significant digits and less significant digits corresponding to said combined more significant digits and less significant digits included in said certain fourth pulse sets, first additional sets of combined more significant digits and less significant digits corresponding to said combined more significant digits and less significant digits included in said fifth pulse sets, and second additional sets of combined more significant digits and sequential ''''1,'''' ''''0'''' and ''''0'''' logic signals corresponding to said respective other fourth pulse sets including combined more significant digits and sequential ''''1,'''' ''''0'''' and ''''0'''' logic signals.

Claim 14

The receiver according to claim 9 in which said utilizing means includes a utilizing circuit for translating said sixth pulse sets into a reproduction of said analog signal varying in magnitude.

Claim 15

The receiver according of claim 6 in which said utilizing means includes: means for decoding said rearranged fourth pulse sets to provide time rearranged fifth pulse sets corresponding to said certain and other sets of said fourth sets and to omit pulses corresponding to said ''''0'''' sets in said fourth sets; and means for translating said fifth pulse sets to reproduce said analog signal varying in magnitude.

Claim 16

The receiver according to claim 11 in which said translating means includes: means for delaying a first portion of said fifth pulse set by a first 1-digit time interval; means for delaying a second portion of said 1-digit delayed first portion of said fifth pulse sets; means for adding said first and second 1-digit delayed first portion of said fifth pulse sets and a second portion of said fifth pulse sets to produce sum samples thereof; means for dividing said sum samples to produce mean pulse samples; means responsive to said ''''0'''' and ''''1'''' signals included in said third pulse sets for converting said mean pulse samples into interpolation pulse samples to represent said omitted pulses in said fifth pulse sets; means for combining a second portion of said 1-digit delayed first portion of said fifth pulse sets and said interpolation pulse samples to produce a sixth set of pulses whose envelope represents the envelope of said analog signal; and means for utilizing said sixth pulse set to reproduce said analog signal.