Abstract Gate circuits are allocated to the evaluating circuits in the evaluating translator unit. These gate circuits are provided with current via low-resistance secondary paths before evaluation. The gates circuits are connected to the outputs of a counting chain adapted to block the low-resistance secondary paths of the gate circuits, individually in succession, for the purposes of evaluation. The interrogation of the translator outputs involves no significant new building up processes, since only one translator output loads the corresponding row resistor at a time. Further gate circuits are assigned to the evaluating circuits. The pulse responsible for indexing the counting chain is fed, via a time-lag component, to these gate circuits. This measure ensures that no invalid output information is indicated during the short period before the occurrence of blocking.
Inventors
👤 Willi Verstegen
Bibliographic Details
Application Number—
JurisdictionUS
Data Sourcegoogle_patents
Last Synchronized2026-11-01 18:49
CPC Classifications
H; H04; H04Q; H04Q3/00
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
115 words
A translator having information data distribution means comprising a jumper field for input information, a jumper field for output information, and a central controlling and evaluating means, said central means comprising a counting chain, gate circuits allocated to individual evaluating circuits in the evaluating means, said gate circuits normally being provided with current via low-resistance secondary paths, means connecting the outputs of said gate circuits to the respective outputs of said counting chain, and means connecting the outputs of said counting chain to the inputs of said gate circuits for successively blocking the low-resistance secondary paths of the respective gate circuits individually on receipt of outputs from said counting chain for the purposes of evaluation.
Claim 2
Dependent Claim
115 words
A translator having information data distribution means comprising a jumper field for input information, a jumper field for output information, and a central controlling and evaluating means, said central means comprising a counting chain, gate circuits allocated to individual evaluating circuits in the evaluating means, said gate circuits normally being provided with current via low-resistance secondary paths, means connecting the outputs of said gate circuits to the respective outputs of said counting chain, and means connecting the outputs of said counting chain to the inputs of said gate circuits for successively blocking the low-resistance secondary paths of the respective gate circuits individually on receipt of outputs from said counting chain for the purposes of evaluation.
Claim 3
Dependent Claim
41 words
The translator claimed in claim 1 and further gate circuits assigned to the respective evaluating circuits, and timer means for enabling or inhibiting said last-mentioned gate circuits a predetermined period of time after the receipt of outputs from said counting chain.