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US3620833A Expired / Lapsed US ⏱️ 0.0 years remaining

Integrated circuit fabrication

Assignee: Texas Instruments Inc
•
Filing: 1966-12-23
•
Granted: 1971-11-16
•
Expires: 1986-12-23
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Abstract

Abstract An integrated circuit structure having a plurality of monocrystalline semiconductor islands separated by a layer of dielectric insulation is fabricated by a method which begins with the formation of a plurality of nucleation sites upon a supported layer of insulating material. A single crystallite of semiconductor material is then vapor deposited at each of the nucleation sites. The crystallites are then covered by the vapor deposition of a second layer of dielectric material. The second layer of dielectric material is then supported by the deposition of a substrate material, followed by removal of the original supporting body to expose the first layer of insulating material, thereby providing a plurality of electrically isolated regions of single crystallite semiconductor material embedded in a suitable substrate. The structure is then completed by forming and interconnecting desired circuit components within the single crystallites.

Inventors

  • 👤 Paul S Gleim
  • 👤 Kenneth E Bean

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 10:59
CPC Classifications
H; H10; H10P; H10P95/00; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/019; H10W10/10; Y; Y10; Y10S; Y10S148/00; Y10S148/043; Y10S148/085; Y10S148/115; Y10S148/122; Y10S148/152; Y10S438/00; Y10S438/974; Y10S438/977

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 23 words
The method as described in claim 1 wherein said nucleation sites are provided by selective damaging of the said layer of insulating material.
Claim 2
Dependent Claim 16 words
The method as described in claim 2 wherein said selective damaging is by an electron beam.
Claim 3
Independent Claim 150 words
A method for producing an integrated circuit structure having a plurality of single crystallites on a single substrate electrically isolated from said substrate and from one another by a layer of dielectric material, composing the steps of: a. forming a layer of silicon dioxide insulating material upon a supporting body, b. forming a plurality of nucleation sites upon said layer of insulating material, c. vapor depositing single crystallites of silicon semiconductor material at each of said nucleation sites, d. depositing a layer of dielectric material upon said single crystallites, e. depositing a substrate of polycrystalline semiconductor material upon said layer of dielectric material, f. etching said supporting body to expose said layer of silicon dioxide, thereby to leave said single crystallites on said substrate electrically isolated from one another and said substrate by said layer of dielectric material, and g. forming individual circuit components within each of said single crystallites.
Claim 4
Dependent Claim 22 words
The method as described in claim 4 wherein said nucleation sites are provided by selective damaging of the said silicon dioxide layer.

References Cited (Backward Citations)

US3326729A Cited
US3364087A Cited
US3390012A Cited
US3332137A Cited
US3381182A Cited
US3385729A Cited
US3372063A Cited
US3391023A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1974-11-15 1975-05-17 1975-11-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1978-11-15 1979-05-17 1979-11-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1982-11-15 1983-05-17 1983-11-16 $7700.00 Window Closed / Lapsed

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