Data processing system

Claim 2

A data processing system for receiving and transmitting clean data, comprising an input for receiving data blocks of digits which may include erroneous digits, and an output terminal at which clean data is applied to a recorder means, comprising means for detecting a received erroneous digit; means coupled to said detector means and responsive to the detected erroneous digit for demanding retransmission of the same data block; first counting means for counting the amount of data sent to the output and thereby recording the position of the erroneous digit in the block; first counting means for counting the amount of data sent to the output and thereby recording the position of the erroneous digit in the block; second counting means for recording the position of each data digit during retransmission; and gating means connected to said first and second counting means for supplying the retransmitted clean digit to said output media after the contents of said counting means coincides with each other.

Claim 3

A data processing system in which blocks of digits are passed, digit by digit, from an input to an output through a reader parity check which stops transmission of said digits when an erroneous one is detected, and which also provides an error signal when said erroneous digit is detected, comprising first and second gates having their inputs connected to the reader; first and second digital counters connected to the outputs of the first and second gates respectively, for selectively counting the number of digits of the reader; a comparator connected to the counters for comparing the numbers therein and providing a compared signal that they are in a predetermined relation; a binary error indicator having a pair of inputs and at least one output, said first input being connected to the reader for receiving said error signal and adapted to render the binary in a first condition in response to said error signal, said second input being connected to the comparator for receiving the compared signal and adapted to render the binary in a second condition in response to said signal, and said output being connected in conjugate relationship to the first and second gates whereby said first gate is enabled when said binary is in its second condition, and said second gate is enabled when said binary is in its first condition, said output also applying a retransmit block request in response to an error signal for initiating retransmittal of the data block; and a circuit connection to the reader to restart transmission of said digits in response to said compare signal; whereby said first gate is enabled by the binary and said first counter counts the number of digits in a block up to the detection of an erroneous digit, after which said binary is rendered in its first condition and the first gate is disabled and the second gate is enabled, and the second counter counts the number of digits of the retransmitted block until it is coincident with the number of correct digits of the original block, then the compare signal is provided, and the error indicator binary switches states and the first counter continues counting until the detection of another erroneous digit.

Claim 4

A data processing system in which blocks of digits are passed, digit by digit, from an input to an output through a reader parity check which stops transmission of said digits when an erroneous one is detected, and which also provides an error signal when said erroneous digit is detected, comprising first and second gates having their inputs connected to the reader; first and second digital counters connected to the outputs of the first and second gates respectively, for selectively counting the number of digits of the reader; a comparator connected to the counters for comparing the numbers therein and providing a compared signal that they are in a predetermined relation; a binary error indicator having a pair of inputs and at least one output, said first input being connected to the reader for receiving said error signal and adapted to render the binary in a first condition in response to said error signal, said second input being connected to the comparator for receiving the compared signal and adapted to render the binary in a second condition in response to said signal, and said output being connected in conjugate relationship to the first and second gates whereby said first gate is enabled when said binary is in its second condition, and said second gate is enabled when said binary is in its first condition, said output also applying a retransmit block request in response to an error signal for initiating retransmittal of the data block; and a circuit connection to the reader to restart transmission of said digits in response to said compare signal; whereby said first gate is enabled by the binary and said first counter counts the number of digits in a block up to the detection of an erroneous digit, after which said binary is rendered in its first condition and the first gate is disabled and the second gate is enabled, and the second counter counts the number of digits of the retransmitted block until it is coincident with the number of correct digits of the original block, then the compare signal is provided, and the error indicator binary switches states and the first counter continues counting until the detection of another erroneous digit.