US3617902A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Frequency multiplier
Assignee: General Electric Co
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Filing: 1970-08-04
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Granted: 1971-11-02
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Expires: 1990-08-04
Abstract
Abstract A frequency multiplier which comprises a voltage-controlled oscillator the output of which is controlled by differential integrator. First and second bistable logic circuits are connected to the inputs of the integrator. The first bistable logic circuit changes its state in response to an input pulse to produce a control voltage for the oscillator from the integrator. A feedback loop from the oscillator to the second bistable circuit includes a counter coupled to the second bistable logic circuit to change the state of the second bistable logic and resets the first circuit after a predetermined number of output pulses. This sequence controls the input level to the voltagecontrolled oscillator, and hence the multiplication factor of the circuit.
Inventors
- 👤 Douglas M Bauer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 20:02
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/183; H03L7/191; H03L7/08; H03L7/085; H03L7/089
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
208 words
A frequency multiplier comprising, in combination: a. a first switching means having an input for coupling to a source of input frequency and an output assuming a first state in the absence of an input signal and a second state in response to an input signal; b. a second switching means having an input and an output, said second switching means assuming a first state in the absence of an input thereto and a second state in response to an input; c. resetting means for resetting said first and second switching means to their first state when both of said switching means assume their second state; d. integrating means having first and second inputs respectively connected to said first and second switching means, said integrating means providing an output indicative of the difference of the inputs applied thereto; e. a voltage-controlled oscillator having an input coupled to the output of said integrating means and having an output for connection to an output frequency utilization means; and f. counting means coupled between the output of said voltagecontrolled oscillator and the input of said seCond switching means for providing an input to said second bistable logic circuit in response to a predetermined number of pulses used by said voltage-controlled oscillator.
Claim 2
Dependent Claim
208 words
A frequency multiplier comprising, in combination: a. a first switching means having an input for coupling to a source of input frequency and an output assuming a first state in the absence of an input signal and a second state in response to an input signal; b. a second switching means having an input and an output, said second switching means assuming a first state in the absence of an input thereto and a second state in response to an input; c. resetting means for resetting said first and second switching means to their first state when both of said switching means assume their second state; d. integrating means having first and second inputs respectively connected to said first and second switching means, said integrating means providing an output indicative of the difference of the inputs applied thereto; e. a voltage-controlled oscillator having an input coupled to the output of said integrating means and having an output for connection to an output frequency utilization means; and f. counting means coupled between the output of said voltagecontrolled oscillator and the input of said seCond switching means for providing an input to said second bistable logic circuit in response to a predetermined number of pulses used by said voltage-controlled oscillator.
Claim 3
Dependent Claim
21 words
A frequency multiplier according to claim 1 in which said integrating means comprises a differential integrator having inverting and noninverting inputs.
Claim 4
Dependent Claim
18 words
The frequency multiplier according to claim 2 in which said first and second switching means comprise J-K flip-flops.
Claim 5
Dependent Claim
54 words
The frequency multiplier according to claim 3 in which potentials having a logic level of 1 are connected to the J and K inputs of said first and second switching means, and the input signal and counting means output are respectively connected to the clock input terminals of said first and second switching means.
Claim 6
Dependent Claim
50 words
A frequency multiplier according to claim 4 in which said resetting means comprises a first NAND-gate having first and second inputs coupled to the outputs of said first and second switching means respectively and having an output terminal connected to the resetting inputs of said first and second switching means.
Claim 7
Dependent Claim
75 words
A frequency multiplier according to claim 5 in which said resetting means further comprises a second NAND gate and a delaying means connected in series between said first NAND gate and the resetting terminal of said first switching means, a one-shot flip-flop connected between said counting means and a second input terminal of said second NAND gate, and delaying means connected between said first NAND gate and the resetting terminal of said second switching means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-11-01 | 1975-05-03 | 1975-11-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-11-01 | 1979-05-03 | 1979-11-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-11-01 | 1983-05-03 | 1983-11-02 | $7700.00 | Window Closed / Lapsed |