Process of producing an array of integrated circuits on semiconductor substrate

Claim 2

The process of claim 2 in which the light-responsive pattern defining medium is photoresist.

Claim 3

A process for the manufacture of an array of integrated circuits on a semiconductor wafer using masks to define areas of each circuit in a plurality of successive process steps, comprising: a. determining the average number of defects in the masks for each process step, b. establishing a first number of masks for one of the process steps, c. determining the number of good integrated circuits in the array that can be obtained with the first number of masks, on the basis of the relationship: wherein: Y is the total number of integrated circuits in the array, g is the number of defect-free integrated circuits in the array that can be obtained if mask matching is carried out, d is the average number of defects in the masks for the process step, and N is the number of masks in the first inventory of masks, d. establishing a second inventory of masks for another one of the process steps sufficient to give at least the same number of good integrated circuits in the array as the first inventory of masks, on the basis of the above relationship, e. inspecting the masks in the inventories so established to determine the location of defects thereon, f. recording the location of the mask defects, g. comparing the location of the mask defects in masks for the plurality of process steps, h. selecting a particular combination of one mask for each of the plurality of successive process steps which will minimize the number of defective integrated circuits in the array, and i. carrying out the successive process steps, using one mask from the selected combination for each successive process step, to define a part of each integrated circuit in a light-responsive pattern defining medium.

Claim 4

The process of claim 4 in which the comparison of defect locations and selection of a mask combination is made by: a. selecting a mask from those for a first one of the steps, b. thereafter comparing the location of defects in masks from those for a second one of the steps with the location of defects in the mask for the first step selected, c. then selecting a mask from those for the second step to maximize the number of defect-free positions in the combination of first and second step masks, d. thereafter comparing the location of defects in masks from those for a third step with the location of defects in the combination of first and second step masks selected, and e. then selecting a mask from those for the third step to maximize the number of defect-free positions in the combination of first, second, and third step masks.

Claim 5

The process of claim 4 in which the light-responsive pattern defining medium is photoresist.

Claim 6

A process for preparing an array of monolithic integrated circuits on a semiconductor wafer, using a plurality of masks in levels for successive processing steps to define parts of the integrated circuits, the integrated circuits being subject to randomly occurring defects caused by random defects in the masks, comprising: a. fabricating a number of masks for each level, b. determining the average number of randomly-occurring defects in the masks for each level, c. determining the number of masks for each level required to give a certain number of defect-free circuits on the wafer if mask matching is carried out, the number corresponding substantially to that which may be obtained with the relationship: wherein: Y is the total numbeR of integrated circuits in the array, g is the number of defect-free integrated circuits in the array that can be obtained if mask matching is carried out, d is the average number of defects in the masks for the process step, and N is the number of masks required for a level, d. adjusting the number of masks available for each level to give at least the number of defect-free circuits in step c) for each level, e. determining the location of defects in the masks, f. comparing the location of the defect-free pattern areas in the masks, g. selecting a combination of one mask from each level to maximize the number of defect-free circuits produced on the wafer, h. coating the semiconductor wafer with a photoresist, i. using a first mask from the selected combination to expose the photoresist, j. carrying out the remainder of a first processing step on the semiconductor wafer, k. coating the semiconductor wafer with photoresist a second time, l. using a second mask from the selected combination to expose the photoresist, m. carrying out the remainder of a second processing step on the semiconductor wafer, and n. continuing the plurality of processing steps on the semiconductor wafer using the remaining masks from the selected combination to expose photoresist on the semiconductor wafer.