Process of producing an array of integrated circuits on semiconductor substrate

Claim 2

The process of claim 1 additionally comprising the steps of: f. after selecting the combination of the first level mask and the second level mask, comparing the location of defects in masks from a third level with the location of defects in only the combination of the first and second level masks selected, g. then selecting a third level mask to maximize the number of defect-free positions in the combination of first, second and third level masks, and h. using the third level mask so selected in one of said successive processing steps for defining a part of each integrated circuit in a light-responsive pattern defining medium.

Claim 3

The process of claim 1 wherein the light-responsive pattern defining medium is photoresist.

Claim 4

a process for producing an array of integrated circuits on a semiconductor wafer using a plurality of masks in different levels to define a part of each integrated circuit in successive processing steps, the integrated circuits being subject to randomly occurring defects caused by random defects in the masks, comprising: a. fabricating a number of masks for each level, b. selecting a mask from a first level, c. thereafter comparing the location of defects in masks from a second level with the location of defects in the first level mask selected, d. then selecting a second level mask to maximize the number of defect-free positions produced by the combination of first and second level masks, e. thereafter comparing the location of defects in masks from a third level with the location of defects in the combination of first and second level masks selected, f. then selecting a third level mask to maximize the number of defect-free positions produced by the combination of first, second and third level masks, nd g. using the combination of masks so selected for defining successively a portion of each integrated circuit in a light-responsive pattern defining medium in each of said successive processing steps.

Claim 5

The process of claim 5 wherein the semiconductor substrate is silicon and the integrated circuits in the array are essentially identical.

Claim 6

The process of claim 5 additionally comprising the steps of: h. after selecting the third level masks, comparing the location of defects in masks for the remaining levels in the process with the location of the defects in masks for the levels already selected, i. selecting masks for the remaining levels to maximize The number of defect-free positions produced by the combination of masks selected, and j. using one of the selected masks for each of the remaining levels for defining successively a portion of each integrated circuit in a light-responsive pattern defining medium in each of the remaining levels in the process.

Claim 7

The process of claim 5 wherein the light-responsive pattern defining medium is photoresist.

Claim 8

A process for the manufacture of an array of monolithic integrated circuits on a semiconductor wafer using masks to define areas of the circuits in a plurality of successive processing steps, which comprises: a. fabricating a set of masks for each processing step, the masks for each processing step having the same predetermined pattern, b. inspecting the masks to determine the location of defects thereon, c. recording the location of the defects in the masks, d. then selecting one mask from a first set of masks for one of the processing steps, e. thereafter comparing the defect locations of masks from a second set of masks for a different processing step with only the defect locations in the mask selected from the first set, f. then selecting a mask from the second set which will minimize the number of additional defective integrated circuits in the array, g. thereafter comparing the defect locations of masks from a third set of masks for another processing step with only the defect locations in the combination of masks selected from the first and second set, h. then selecting a mask from the third set which will minimize the number of additional defective integrated circuits in the array when combined with the first and second masks selected, and i. using the masks so selected, one for each successive processing step, to define successively an area of each circuit in a light-responsive pattern defining medium in each of the plurality of processing steps.

Claim 9

The process of claim 9 additionally comprising the steps of: j. successively comparing the defect locations of masks for each remaining processing step with only the defect locations in masks for the processing steps already selected, k. selecting a mask for each remaining processing step which, on the basis of the comparison with the defect locations in masks for the processing steps already selected, will minimize the number of additional defective integrated circuits in the array produced by the selected mask for each remaining processing step, and l. using the masks for the remaining processing steps so selected, one for each processing step, to define successively an area of each circuit in a light-responsive pattern defining medium in each of the remaining processing steps.

Claim 10

A process for preparing an array of monolithic integrated circuits on a semiconductor wafer, using a plurality of masks in successive processing steps to define parts of the integrated circuits, the integrated circuits being subject to randomly occurring defects caused by random defects in the masks, comprising: a. fabricating a number of masks for each processing step, b. inspecting each mask to determine which random positions in the array contain defects in the masks, c. recording the random defects for each mask on suitable recording medium, d. selecting one mask from a first set of masks each having the same predetermined pattern for one of the processing steps, e. coating the semiconductor wafer with a photoresist, f. using the selected mask from the first set to expose the photoresist, g. carrying out the remainder of a first processing step on the semiconductor wafer, h. thereafter comparing the defect locations of masks from a second set of masks each having the same predetermined pattern for a different processing step with the defect locations in the mask selected from the first set, i. then selecting a mask from the second set which will minimize the number of additional defective integrated circuits produced in array, j. coating the semiconductor wafer with photoresist a second time, k. using the mask selected from the second set to expose the photoresist, l. carrying out the remainder of a second processing step on the semiconductor wafer, m. thereafter comparing the defect locations of masks from a third set of masks each having the same predetermined pattern for another processing step with the defect locations in the combination of masks selected from the first and second set, n. then selecting a mask from the third set which will minimize the number of additional defective integrated circuits produced in the array when combined with the first and second masks selected, o. coating the semiconductor wafer with photoresist a third time, p. using the mask selected from the third set to expose the photoresist, q. carrying out the remainder of a third processing step on the semiconductor wafer, r. thereafter comparing the defect locations of a mask for each remaining processing step with the defect locations in the masks for the processing steps already selected, s. after comparing defect locations in the masks for each remaining processing step with the defect locations in masks already selected, selecting a mask for that remaining processing step which will minimize the number of additional defective integrated circuits in the array produced by the selected mask for that remaining processing step, and t. continuing the plurality of processing steps on the semiconductor wafer using each mask so selected to expose photoresist on the semiconductor wafer.