US3614636A
Expired / Lapsed
US
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Distortion correction circuit for linearly distorted pulse sequences
Assignee: Individual
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Filing: 1969-09-26
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Granted: 1971-10-19
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Expires: 1989-09-26
Abstract
Abstract A circuit for correcting linear distortions in a received signal pulse train by converting the pulse train into a signal sequence by periodically sampling the received train and storing each sample value until the next sampling, quantizing the sequence in discrete amplitude levels identical with those of the initial pulse train, sequentially delaying the quantized sequence, multiplying each delayed sequence by a correction value, adding all multiplied sequences to the initial sequence at the quantizing input, and modifying the correction values in a direction to establish equality between the sequence values before and after quantizing.
Inventors
- 👤 Broder Wendland
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 15:55
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/03; H04L25/03006; H04L25/03012; H04L25/03114; H04L25/03146
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
192 words
In a distortion correction circuit for correcting linear distortions imparted during transmission to a signal pulse train composed of pulses having a predetermined number of discrete amplitude levels, which circuit includes: time delay means having an input and a plurality of outputs for imparting successive delays to a signal applied to its input and for delivering each successively delayed signal to a different respective output; a plurality of evaluation members each having an input connected to a respective output of said time delay means for modifying the signal applied to its input by a factor having an adjustable value; and summing means connected to receive the output signals from all of said evaluation members, the improvement wherein said summing means are also connected to receive a signal sequence obtained by periodically sampling the distorted signal pulse train and storing each sampled value until the next sampling, and wherein said circuit comprises quantization means connected between the input of said circuit and the input of said delay means for quantizing the signal which it receives into a predetermined number of discrete amplitude levels identical to those of the signal pulse train before distortion.
Claim 2
Dependent Claim
192 words
In a distortion correction circuit for correcting linear distortions imparted during transmission to a signal pulse train composed of pulses having a predetermined number of discrete amplitude levels, which circuit includes: time delay means having an input and a plurality of outputs for imparting successive delays to a signal applied to its input and for delivering each successively delayed signal to a different respective output; a plurality of evaluation members each having an input connected to a respective output of said time delay means for modifying the signal applied to its input by a factor having an adjustable value; and summing means connected to receive the output signals from all of said evaluation members, the improvement wherein said summing means are also connected to receive a signal sequence obtained by periodically sampling the distorted signal pulse train and storing each sampled value until the next sampling, and wherein said circuit comprises quantization means connected between the input of said circuit and the input of said delay means for quantizing the signal which it receives into a predetermined number of discrete amplitude levels identical to those of the signal pulse train before distortion.
Claim 3
Dependent Claim
31 words
An arrangement as defined in claim 1 wherein said delay means are constituted by a shift register whose shift rate is synchronized with the periodic sampling of the signal pulse train.
Claim 4
Dependent Claim
43 words
An arrangement as defined in claim 2 further comprising subtraction means having respective inputs connected to the input and output of said quantization means and an output at which appears an error signal proportional to the difference between the signals at its inputs.
Claim 5
Dependent Claim
88 words
An arrangement as defined in claim 3 wherein each said evaluation member comprises: a first multiplier having one input connected to said subtraction means output and another input connected to said respective output of said time delay means; an integrator having its input connected to the output of said first multiplier; and a second multiplier having one input connected to the output of said integrator, another input connected to said respective output of said time delay means, and its output connected to the input of said summing means.
Claim 6
Dependent Claim
21 words
An arrangement as defined in claim 4 wherein at least one of said multipliers is composed of a field effect transistor.
Claim 7
Dependent Claim
22 words
An arrangement as defined in claim 1 wherein said quAntization means has its input connected to the output of said summing means.
Claim 8
Dependent Claim
42 words
An arrangement as defined in claim 1 further comprising means connected to the input of said summing means for periodically sampling the distorted signal pulse train and storing the sampled values, and for delivering the resulting signal sequence to said summing means.
References Cited (Backward Citations)
DE1157677B
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-10-18 | 1975-04-19 | 1975-10-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-10-18 | 1979-04-19 | 1979-10-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-10-18 | 1983-04-19 | 1983-10-19 | $7700.00 | Window Closed / Lapsed |