Computer utilizing random pulse trains

Claim 2

A computing device comprising means including a click pulse source and noise supply means interconnected to generate a plurality of input trains of synchronous pulses, the pulses occurring in said trains independently of each other and at intervals of random duration, and logic means controlled by the input trains of pulses for producing an output train of pulses in which each output pulse occurs in accordance with a predetermined logical function of the presence values of the pulses in the input trains.

Claim 3

A computing device as defined in claim 1 wherein said logic means comprises an AND gate having a plurality of input legs to which the respective input trains of pulses are applied whereby pulses occur in the output train at an average rate which is proportional to the arithmetic product of the average rates of occurrence of pulses in the input trains.

Claim 4

In a computing device as defined in claim 2, means for independently establishing the average frequencies of occurrence of pulses in the respective input trains at values approximately equal to the values of a plurality positive numbers that are to be multiplied, where each of the numbers is no greater than 1.0.

Claim 5

A computing device as defined in claim 3 including means for independently indicating the average frequency of occurrence of pulses in the output train of pulses.

Claim 6

A computing device as defined in claim 4 including means for indicating the average frequency of occurrence of pulses in the input trains of pulses.

Claim 7

In a random pulse generator defined in claim 1 wherein said clock pulse source supplied clock pulses at regular intervals.

Claim 8

In a computing device: a source of clock pulses that occur at successive times, a plurality of sources of successively occurring noise signals of variable amplitudes, a plurality of random pulse generators, all controlled by said clock pulse source, and each respectively controlled by pulses from the respective noise signal sources for producing a corresponding train of randomly occurring pulses, each of which occurs only when the amplitude of the noise signal supplied to the respective generators lies in a predetermined range during the occurrence of a clock pulse, and logic means controlled by said trains of pulses for producing an output train of pulses in which each pulse occurs in accordance with a predetermined logical function of the presence values of the pulses in the input trains.

Claim 9

In a computing device: a source of clock pulses that occur at successive times, a plurality of sources of successively occurring noise signals of variable amplitudes, a plurality of random pulse generators, all controlled by said clock pulse source, and each respectively controlled by pulses from the respective noise signal sources for producing a corresponding train of randomly occurring pulses, each of which occurs only when the amplitude of the noise signal supplied to the respective generators lies in a predetermined range during the occurrence of a clock pulse, and logic means controlled by said trains of pulses for producing an output train of pulses in which each pulse occurs in accordance with a predetermined logical function of the presence values of the pulses in the input trains.

Claim 10

In a computing device as defined in claim 7 wherein the said output pulses in each of said pulse trains have different amplitudes, and comprising a plurality of means for producing pulses in the output of the respective random pulse generators only when the amplitude of the noise signals applied to said respective generator lies above a predetermined level.

Claim 11

In a computing device as defined in claim 7 wherein each random pulse generator comprises a threshold circuit for producing output pulses in said generator only when the amplitude of noise occurring at some point in said generator lies above a predetermined threshold.

Claim 12

In a computing device as in claim 9 wherein each said random pulse generator comprises means for adjusting the threshold established by the threshold circuit in said random pulse generator whereby the average rate at which pulses occur in the output of the threshold circuit may be varied.

Claim 13

In a computing device as in claim 10 wherein each said random pulse generator comprises means for indicating the average rate at which pulses are occurring in each random pulse generator and the average rate at which pulses are occurring in the output of said logic means.

Claim 14

In a computing device as defined in claim 11 wherein said logic means comprises an AND gate to which pulses are applied from the random pulse generators whereby the average rate at which pulses appear in the output train is the arithmetic product of the average rates at which pulses appear in the respective input trains.

Claim 15

In a computing device, a source of clock pulses that occur at successive times, a plurality of random pulse generators controlled by said clock pulse source for generating a corresponding plurality of first trains of synchronous pulses, said pulses occurring in the respective trains only at times predetermined by said clock pulse source, the pulses in the respective first trains being of random amplitude, means connected with each generator including a threshold circuit for converting the pulses in each first train into a corresponding second train of pulSes of random frequency by removing from each first pulse train only pulses that have amplitudes below a corresponding threshold, and means including logic means controlled by pulses of said second trains for producing an output train of pulses in which each pulse occurs in accordance with a predetermined logical function of the presence values of pulses in said second trains.

Claim 16

In a computing device, a source of clock pulses that occur at successive times, a plurality of random pulse generators controlled by said clock pulse source for generating a corresponding plurality of first trains of synchronous pulses, said pulses occurring in the respective trains only at times predetermined by said clock pulse source, the pulses in the respective first trains being of random amplitude, means connected with each generator including a threshold circuit for converting the pulses in each first train into a corresponding second train of pulSes of random frequency by removing from each first pulse train only pulses that have amplitudes below a corresponding threshold, and means including logic means controlled by pulses of said second trains for producing an output train of pulses in which each pulse occurs in accordance with a predetermined logical function of the presence values of pulses in said second trains.

Claim 17

In a computing device as defined in claim 13 wherein each random pulse generator comprises a threshold circuit for producing output pulses in said generator only when the amplitude of noise occurring at some point in said generator lies above a predetermined threshold.

Claim 18

In a computing device as in claim 14 wherein each said random pulse generator comprises means for adjusting the threshold established by the threshold circuit therein whereby the average rate at which pulses occur in the second trains of pulses developed by said each random pulse generator may be varied.

Claim 19

In a computing device as in claim 15 wherein each said random pulse generator comprises means for indicating the average rate at which pulses are occurring in each random pulse generator and the average rate at which pulses are occurring in the output of said logic means.

Claim 20

In a computing device as defined in claim 15 wherein said logic means comprises an AND gate to which pulses of said second trains are applied from the random pulse generators whereby the average rate at which pulses appear in the output train is the arithmetic product of the average rates at which pulses appear in the respective second trains.