US3611050A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase sequence and phase loss monitor
Assignee: Sycon Corp
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Filing: 1970-06-25
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Granted: 1971-10-05
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Expires: 1990-06-25
Abstract
Abstract Solid-state circuitry offering protection to electrical and electronic equipment from incorrect phase sequence connection, low voltage or a phase failure on a three-phase power system. If phasing is correct and full line voltage is present on all three phases, an internal control relay is energized, where, in a contrary situation, the aforesaid control relay becomes deenergized. The monitor represents an important safety device where connection to the powerline is critical, or where loss of voltage or of one or more phases may cause damage to electrical equipment.
Inventors
- 👤 Clement J Weber
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 17:12
CPC Classifications
H; H02; H02H; H02H11/00; H02H11/004; H02H3/00; H02H3/24; H02H3/253
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
116 words
A monitor circuit for a three-phase power system comprising a first line, a second line and a third line, a first resistor interconnecting said first line and said second line, a second resistor interconnecting said second line and said third line, said second line including a first capacitor connecting between said first resistor and said second resistor, a third resistor in series with said second resistor between said second line and said third line, a second capacitor bypassing said third resistor, a relay, means developing a voltage across said relay, switching means responsive to a voltage of said third resistor, and solid-state means responsive to voltage developed across said second capacitor energizing said relay after switching.
Claim 2
Dependent Claim
116 words
A monitor circuit for a three-phase power system comprising a first line, a second line and a third line, a first resistor interconnecting said first line and said second line, a second resistor interconnecting said second line and said third line, said second line including a first capacitor connecting between said first resistor and said second resistor, a third resistor in series with said second resistor between said second line and said third line, a second capacitor bypassing said third resistor, a relay, means developing a voltage across said relay, switching means responsive to a voltage of said third resistor, and solid-state means responsive to voltage developed across said second capacitor energizing said relay after switching.
Claim 3
Dependent Claim
28 words
The monitor circuit of claim 1 where said first resistor, said second resistor and said first capacitor each have an equal ohmic value at the frequency of operation.
Claim 4
Dependent Claim
16 words
The monitor circuit of claim 1 where a time delay means is provided for said relay.
Claim 5
Dependent Claim
14 words
The monitor circuit of claim 1 where said relay is energized during normal operation.
Claim 6
Dependent Claim
16 words
The monitor circuit of claim 1 where said solid-state means has a gate biased to ground.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-10-04 | 1975-04-05 | 1975-10-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-10-04 | 1979-04-05 | 1979-10-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-10-04 | 1983-04-05 | 1983-10-05 | $7700.00 | Window Closed / Lapsed |