Associative memory cell with interrogation on normal digit circuits

Claim 2

In combination, at least one storage means having at least two stable states of operation, each state representing a different type of information, a pair of terminals in said bistable storage means for receiving input information signals to determine the state of said storage means and for providing at the same terminals output information signals representing the current stable state of said storage means, circuit means supplying both said input information signals and additional information siGnals and for receiving said output signals, gate means selectively operable to couple said input information signals from said circuit means to said terminals and to exclude said additional information signals from said terminals, and means coupled between said circuit means and said terminals for comparing said excluded signals with said output signals to indicate said current stable state in relation to said excluded signals.

Claim 3

The combination in accordance with claim 1 in which said storage means includes circuits coupling operating current thereto at a first voltage, a match circuit is provided, switch means couple an output of said comparing means to said match circuit, said switch means having a predetermined voltage threshold for initiating operation and which is much smaller than said first voltage, and said match circuit includes means supplying operating current to said switch means at a second voltage which is somewhat greater than said threshold voltage but much smaller than said first voltage.

Claim 4

The combination in accordance with claim 1 in which means independent of said circuit means are provided for supplying operating current to said storage means.

Claim 5

The combination in accordance with claim 1 in which said pair of terminals in each of said storage means comprises a pair of circuit points at different complementary voltage levels for representing two different types of information during different stable states of storage means operation, and said circuit means comprise a pair of circuits coupled to respective ones of the circuit points of said pair for each said cell.

Claim 6

The combination in accordance with claim 1 in which said gate means for each storage means comprises a pair of insulated gate field effect transistors coupled between said circuit means and each of said terminals, and means connect gate electrodes of the last-mentioned transistors together.

Claim 7

The combination in accordance with claim 1 in which a plurality of said storage means are arranged in m electrical columns and n electrical rows, said circuit means comprise m circuit pairs, each pair supplying complementary information signals to all gate means of said storage means in a different one of said columns, n circuits are connected for supplying word drive control signals to said gate means of all said storage means of a different one of said rows for coupling said input signals and excluding said additional signals, and n additional circuits each connected to all storage means of a different one of said rows for receiving indicating signals from said comparing means thereof.

Claim 8

The combination in accordance with claim 1 in which said storage means includes at least one connection to which operating potential is supplied, a pair of insulated gate field effect transistors is provided, each of said transistors having a gate electrode which is cross-coupled to an additional electrode of the other transistor, means connect both a gate electrode and another additional electrode of a first one of said cross-coupled transistors to said operating potential terminal, a match circuit is provided, means connect another additional electrode of a second one of said pair of transistors to said match circuit, and means couple said gate electrode of said second transistor to said comparing means to receive the comparing means indication.

Claim 9

The combination in accordance with claim 7 in which said match circuit comprises a further transistor having base, emitter, and collector electrodes, a connection supplying current from said further transistor emitter to said second transistor of each of said storage means in parallel, and a potential source connected in series between said storage means and said base electrode, said potential source being poled for forward conduction of current in said further transistor.

Claim 10

The combination in Accordance with claim 1 in which said storage means, said gate means, and said comparing means all comprise insulated gate field effect transistor circuits.

Claim 11

The combination in accordance with claim 9 in which said insulated gate field effect transistor circuits include transistors which have only wire interconnections.

Claim 12

The combination in accordance with claim 9 in which all of said transistor circuits utilize insulated gate field effect transistors having gate-channel insulation comprising dielectric material laminations of different types of dielectric materials.

Claim 13

The combination in accordance with claim 9 in which said storage means includes a pair of insulated gate field effect transistors which are cross-coupled for bistable circuit operation, and said pair of transistors each has a substantially higher conductance factor than do other transistors of said combination.

Claim 14

The combination in accordance with claim 12 in which said gate means and said comparing means include transistors having conductance factors about 2 1/2 times larger than the conductance factors of said cross-coupled transistors.

Claim 15

The combination in accordance with claim 1 in which said comparing means comprises for each of said storage means a pair of insulated gate field effect transistors connected in series between said gating means for respective ones of said terminals of said storage means, and such series connection having a common terminal between said transistors.

Claim 16

The combination in accordance with claim 14 in which a match circuit is provided, means including an additional insulated gate field effect transistor couple an output of said comparing means to said match circuit, said additional transistor being operable between nonconducting and conducting conditions by the comparing means indication to affect current in said match circuit, said additional transistor having a predetermined source-gate threshold voltage that must be at least attained to support said conducting condition, said additional transistor and said pair of transistors have conductance factors CA and CI, respectively, which are proportioned to satisfy the following relation: VI CI/CA (V0-VD-VT) where VI is the lowest voltage at said additional transistor gate which can turn off said additional transistor, VO is a signal output voltage at the higher voltage one of said terminals of the bistable storage means, VD is the highest signal voltage on said circuit means, and VT is said threshold voltage.

Claim 17

The combination in accordance with claim 14 in which each of said transistors is connected to supply current to said common terminal from said circuit means in response to different information signal states at a respective one terminal of said storage means and at said circuit means.

Claim 18

The combination in accordance with claim 14 in which each of said transistors is connected to supply current to the common terminal from a corresponding one of said terminals of said storage means in response to different information signal states at a terminal of said storage means and at said circuit means.

Claim 19

The combination in accordance with claim 14 in which each of said transistors includes a gate electrode and two additional electrodes, one of said additional electrodes of each of said transistors is connected to said common terminal, and each of said transistors has its gate electrode and the other of its additional electrodes each connected to a different one of said circuit means and one of said storage means terminals.

Claim 20

The combination in accordance with claim 18 in which each of said comparing means transistors has its gate electrode connected to a different one of said terminals of said storage means, and each such transistor has its other Additional electrode connected to said circuit means.

Claim 21

The combination in accordance with claim 18 in which each of said comparing means transistors has its gate electrode connected to said circuit means, and each such transistor has its other additional electrode connected to a different one of said terminals of said storage means.

Claim 22

The combination in accordance with claim 14 in which means including a pair of source terminals supply operating current to said storage means, means connect said common terminal of said series connection to one of said source terminals for developing a potential difference in response to a comparing means signal at said common terminal, a match circuit is provided for conducting current, and switch means are coupled between said common terminal and said match circuit for changing current in said match circuit as a function of said signal at said common terminal.

Claim 23

The combination in accordance with claim 21 in which said switch means comprises a source of current, and an insulated gate field effect transistor coupling the last-mentioned source to said match circuit.

Claim 24

The combination in accordance with claim 22 in which said switch means transistor has a predetermined voltage threshold for initiating transistor conduction, means supply operating current to said storage means and to said switch means transistor, and means in said supply means reducing voltage at which current is supplied to said storage means to a level which is less than voltage at which current is supplied to said switch means transistor by an amount corresponding approximately to twice said threshold voltage.