US3609709A
Expired / Lapsed
US
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Fail-safe memory circuits
Assignee: Trane US Inc
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Filing: 1969-05-19
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Granted: 1971-09-28
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Expires: 1989-05-19
Abstract
Abstract This disclosure relates to fail-safe memory circuits for storing information data comprising a source of recurrent signals which is selectively gated by the presence of a storage command signal and a holding command signal, and an amplified means receiving the gated recurrent signals and producing an output when and only when valid information data is stored.
Inventors
- 👤 Walter W Sanville
- 👤 John O G Darrow
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 17:25
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
98 words
A memory circuit which operates in a fail-safe manner comprising, first fail-safe circuit means for producing recurrent signals in response to the presence of a storage command signal, second fail-safe circuit means coupled to said first circuit means for passing said recurrent signals received from said first circuit means, and third fail-safe circuit means coupled to said second circuit means for amplifying said recurrent signals passed by said second circuit means and for producing an output signal which is indicative of a valid stored information bit when and only when no critical circuit or component failure is present.
Claim 2
Dependent Claim
98 words
A memory circuit which operates in a fail-safe manner comprising, first fail-safe circuit means for producing recurrent signals in response to the presence of a storage command signal, second fail-safe circuit means coupled to said first circuit means for passing said recurrent signals received from said first circuit means, and third fail-safe circuit means coupled to said second circuit means for amplifying said recurrent signals passed by said second circuit means and for producing an output signal which is indicative of a valid stored information bit when and only when no critical circuit or component failure is present.
Claim 3
Dependent Claim
25 words
A memory circuit as defined in claim 1 wherein said first circuit means includes a first gate circuit and an external source of recurrent signals.
Claim 4
Dependent Claim
22 words
A memory circuit as defined in claim 1 wherein said first circuit means includes an oscillating circuit for producing said recurrent signals.
Claim 5
Dependent Claim
39 words
A memory circuit as defined in claim 1 wherein said second circuit means includes an ''''AND'''' gate which passes said recurrent signals only during the presence of a DC holding signal and in the absence of a circuit malfunction.
Claim 6
Dependent Claim
35 words
A memory circuit as defined in claim 1 wherein a feedback means is coupled from said third circuit means to said first circuit means for sustaining storage of the information bit in said memory circuit.
Claim 7
Dependent Claim
26 words
A memory circuit as defined in claim 5 wherein said feedback means includes a blocking diode serially connected between said first and said third circuit means.
Claim 8
Dependent Claim
25 words
A memory circuit as defined in claim 5 wherein said feedback means includes a controllable switching means connected between said first and said third means.
Claim 9
Dependent Claim
34 words
A memory circuit as defined in claim 7 wherein said controllable switching means comprises a normally open contact of a relay which is controlled by the output signal produced by said third circuit means.
Claim 10
Dependent Claim
37 words
A memory circuit as defined in claim 5 wherein said third circuit means produces an AC output signal indicative of the stored information bit and produces a DC feedback signal for sustaining storage of the information bit.
Claim 11
Dependent Claim
18 words
A memory circuit as defined in claim 1 wherein said storage command signal is a DC voltage signal.
Claim 12
Dependent Claim
45 words
A memory circuit as defined in claim 10 wherein said third circuit means includes a DC voltage supply which is of the opposite polarity of said DC voltage signal so that failure of said third circuit means is incapable of simulating a valid information bit.
Claim 13
Dependent Claim
32 words
A memory circuit as defined in claim 11 wherein said DC voltage supply of said third circuit means includes a switching device for providing a controllable holding signal for the memory circuit.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-09-27 | 1975-03-29 | 1975-09-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-09-27 | 1979-03-29 | 1979-09-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-09-27 | 1983-03-29 | 1983-09-28 | $7700.00 | Window Closed / Lapsed |